Inject an inner-layer graphic primitive into a footprint block.

Run a lightweight DFM check using available DRC data.

Estimate fabrication cost from board area, layers, and via count.

Load a bundled manufacturer DFM profile for subsequent checks.

Run a manufacturer-aware DFM review using the active bundled profile.

Export the active custom DRC rules file for sharing or CI.

List known DRC rules from the active .kicad_dru file.

Create or update a custom DRC rule in the active .kicad_dru file.

Delete a custom DRC rule from the active rules file.

Enable or disable a custom DRC rule.

Review whether ICs have nearby decoupling capacitors.

Review diff-pair skew and width symmetry.

Review GND plane presence and a simple void-risk proxy.

Review a high-speed net class for a short-stub proxy.

Check whether a signal has an obvious nearby GND return plane.

Warn when routed signals share layers with split non-ground planes.

Estimate via-stitching density from existing ground vias.

Run a lightweight EMC sweep with at least ten heuristic checks.

Render the board to a PNG image.

Export a STEP model for the active board.

Export a bill of materials.

Export drill files.

Export a board layer to DXF when supported.

Export Gerber manufacturing files.

Export IPC-2581 manufacturing data.

Generate the standard set of manufacturing exports.

Export a KiCad schematic netlist.

Export the PCB to PDF.

Export assembly position data.

Export the schematic to PDF.

Export a SPICE netlist.

Alias for STEP export with an optional explicit output path.

Export a board layer to SVG when supported.

Export board statistics and return a readable preview.

Return only courtyard issues from DRC.

Return silkscreen overlap issues from DRC.

Return only unconnected net issues from DRC.

Create a new minimal KiCad project structure and activate it.

Show the currently configured KiCad project paths.

Get the tool names available in a specific category.

Get KiCad version information and current connection status.

Show a concise startup guide and all tool categories.

List recently opened KiCad projects from KiCad's config files.

List all available tool categories and capabilities.

Scan a directory and report any KiCad project files it contains.

Set the active KiCad project directory and file paths.

Assign a footprint property to a schematic symbol.

Assign an LCSC part code to a schematic symbol property.

Assign a live part (LCSC/MPN) to a schematic symbol and optionally its footprint.

This is the recommended tool for closing the part-selection loop after lib_recommend_part() or lib_search_components() returns a suitable part.

Args: sym_ref: Schematic reference designator (e.g. "U1", "C4"). lcsc_code_or_mpn: LCSC part code or manufacturer part number. auto_assign_footprint: If True, attempts to assign the footprint from the live part data to the symbol. Requires the schematic backend. source: Parts source for detail lookup.

Returns: Confirmation of LCSC/MPN assignment and footprint status.

Check live stock availability for the requested schematic references.

Create a simple custom symbol in the active project directory.

Find nearby alternative parts for the supplied LCSC code.

Generate an IPC-7351B compliant KiCad footprint (.kicad_mod) and save it.

Supported packages: 0201, 0402, 0603, 0805, 1206, 1210, 2512 (chip passives), SOT-23, SOIC, SOP, SSOP, TSSOP (dual SMD), QFP, LQFP, TQFP (quad flat), QFN, DFN (no-lead), BGA (ball grid array), PinHeader (through-hole).

Args: package: Package family name (case-insensitive). density: IPC-7351B density level: A (generous), B (nominal), C (compact). pin_count: Number of leads / balls (required for multi-lead packages). pitch_mm: Lead pitch in mm. body_l_mm: Body length in mm. body_w_mm: Body width in mm (QFP only; defaults to body_l_mm). rows: BGA rows or PinHeader row count (1 or 2). exposed_pad_mm: Exposed pad size for QFN in mm. ball_diameter_mm: BGA ball diameter in mm. output_path: Optional relative path inside output_dir. Defaults to footprints/<package>.kicad_mod.

Returns: Confirmation with the saved file path, or an error message.

Generate a KiCad symbol (.kicad_sym) from a pin table and save it.

Each pin dict must contain: number (str | int), name (str). Optional per-pin keys: pin_type (input/output/bidirectional/passive/power_in/power_out/…), side (left/right/top/bottom), unit (int ≥ 1).

Args: name: Symbol name, used as both the library entry and the default value. pins: List of pin specification dicts. reference_prefix: Ref-des prefix (U, J, Q, R, …). description: Short human description. datasheet: Datasheet URL or path. footprint_hint: Default footprint (e.g. "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"). output_path: Optional relative path inside output_dir. Defaults to symbols/<name>.kicad_sym.

Returns: Confirmation with the saved file path, or an error message.

Generate a live BOM summary with unit and extended pricing.

Return live component detail for a specific LCSC code or MPN.

Return a datasheet URL from the symbol library when available.

Return the configured 3D model path for a footprint.

Return details for a single footprint.

Return details for a single symbol.

List footprints in a specific library.

List configured symbol and footprint libraries.

Rebuild the in-memory symbol search index.

Recommend a purchasable part given electrical requirements.

Args: category: Component category keyword to search (e.g. "LDO regulator", "N-channel MOSFET", "ferrite bead", "ESD protection"). requirements: Dict of electrical parameter hints used for post-search filtering. Common keys: voltage_v, current_a, vgs_v, rds_on_mohm, psrr_db, capacitance_uf, resistance_ohm. Values can be numbers (min) or {"min": x, "max": y} dicts. package: Optional SMD package filter (e.g. "SOT-23", "SOIC-8"). only_basic: Prefer JLCPCB basic parts (lower assembly cost). source: Parts source: "jlcsearch", "nexar", or "digikey". max_results: Maximum number of recommendations to return.

Returns: Ranked list of part recommendations with LCSC code, MPN, package, price.

Search live component sources for purchasable parts.

Search footprint libraries by footprint name.

Search symbol libraries by name, description, or keywords.

Evaluate manufacturing readiness against the active or requested DFM profile.

Report whether the detected KiCad CLI advertises a given board-import format.

Apply JLCPCB CPL rotation corrections to a KiCad-exported pick-and-place CSV.

KiCad exports component orientations relative to its own coordinate system, which differs from what JLCPCB's SMT assembly service expects. This tool reads a CPL CSV (produced by export_pos), applies per-footprint rotation offsets from the bundled jlcpcb_rotations.json table, and writes a corrected CSV ready for direct upload to JLCPCB.

Columns expected (KiCad default CPL export): Ref, Val, Package, PosX, PosY, Rot, Side

Args: cpl_csv_path: Path to the CPL CSV file (relative to project dir). output_path: Output path for the corrected CSV. Defaults to <stem>_jlcpcb_corrected.csv next to the input file. dry_run: If True, return a preview table without writing the file.

Returns: Summary of corrections applied, or a preview table for dry_run.

Generate a SHA256-signed release manifest for the manufacturing package.

Collects all files in the output directory, computes SHA256 hashes, and records tool versions, intent hash, and gate status into a manifest.json and MANIFEST.txt.

Args: output_path: Subdirectory inside the project (defaults to output/).

Returns: Confirmation with manifest path and file count.

Generate a bring-up test plan from the project design intent.

Produces a structured markdown checklist covering:

• Power-on sequence and current limit checks for each power rail.

• Protocol loopback / link-up checks for each interface.

• Critical-net continuity probes.

• Visual inspection items.

Args: output_path: Optional relative path for saving the plan (e.g. "test_plan.md"). If omitted, returns the plan as text only.

Returns: Bring-up test plan in markdown format.

Import an Allegro board into a KiCad project directory.

Import a gEDA PCB into a KiCad project directory.

Import a PADS PCB into a KiCad project directory.

Panelize the active PCB using KiKit.

Creates a panel of multiple boards for efficient PCB fabrication. Requires kikit to be installed (pip install kikit).

Args: layout: Panel layout type: "grid" (rectangular array), "mousebites" (tab+mousebite breakaway), or "vcut" (V-cut scoring). rows: Number of board rows in the panel. cols: Number of board columns in the panel. spacing_mm: Gap between boards in mm. frame_width_mm: Panel frame/rail width in mm. output_path: Optional output file path (relative to output_dir). Defaults to panel/<boardname>_panel_<rows>x<cols>.kicad_pcb.

Returns: Confirmation with the panel file path, or an error message.

Add a production barcode marker to the board file.

Add a blind or buried via between the requested copper layers.

Add a board graphic circle.

Backward-compatible alias for pcb_add_zone().

Append simple fiducial footprints near the board corners.

Add a microvia between adjacent copper layers.

Append standard mounting-hole footprints around the current board frame.

Add a board graphic rectangle.

Add a board graphic segment.

Create small copper helper zones at simple pad-to-track junctions.

Add board text.

Add a single track segment.

Add multiple tracks in a single operation.

Add a via.

Add a copper zone with an arbitrary polygon outline on one copper layer.

Arrange selected footprints into a straight row or column.

Place PCB footprints from the current schematic using deterministic heuristics.

Run a force-directed spring-embedder placement algorithm on a set of components.

This tool computes optimised X/Y positions for components based on their net connectivity without requiring KiCad to be open. Use it to get a placement suggestion, then apply the result with pcb_move_footprint for each component.

Args: component_positions: List of component dicts with keys: ref (str), x (float, mm), y (float, mm), w (float, mm, optional default 2), h (float, mm, optional default 2), fixed (bool, optional default false). nets: List of net dicts with keys: name (str), refs (list[str]), weight (float, optional default 1.0). board_width_mm: Soft boundary width in mm (default 100). board_height_mm: Soft boundary height in mm (default 80). iterations: Number of spring-embedder iterations (default 300). k_spring: Spring attraction coefficient (default 0.4). k_repel: Coulomb repulsion coefficient (default 80.0).

Returns: JSON string with optimised positions for each component.

Generate a BGA fanout via-placement plan (dog-ear or inline strategy).

Returns per-ball via coordinates and suggested track widths so the agent can call pcb_add_via and pcb_add_track to physically fanout the BGA. Actual pad coordinates must come from the board footprint (use pcb_get_pads).

Args: balls: List of ball dicts with keys: row (str, e.g. "A"), col (int, 1-based), net (str), x_mm (float, ball centre X), y_mm (float, ball centre Y). pitch_mm: Ball pitch in mm (e.g. 0.5, 0.65, 0.8, 1.0). via_drill_mm: Via drill diameter in mm (default 0.2). via_annular_mm: Via annular ring width in mm (default 0.1). escape_layer: Inner copper layer to fan out to (default "In1.Cu"). strategy: "dog_ear" (diagonal escape, most common) or "inline" (horizontal escape, for large pitch).

Returns: JSON string with via placement plan for each ball.

Capture a reusable PCB design block from selected footprint references.

List stored PCB design blocks created from selected footprints.

Place a stored PCB design block by cloning its saved footprint blocks.

Run a heuristic creepage clearance review against pad spacing.

Delete items by UUID.

Export the active PCB as a KiCad 10 3D PDF.

Return the current board as a bounded S-expression string.

Summarize the current board.

Read the active board design rules file when available.

List every layer referenced by a footprint block, including inner layers.

List board footprints.

Estimate trace impedance for the supplied width on the named stackup layer.

List enabled board layers.

List all board nets.

List board pads.

Report currently unconnected board items using the latest DRC view.

List currently selected items in the PCB editor.

List graphical board shapes.

Show the current stackup.

List board tracks.

List board vias.

List all board copper zones.

Cluster existing footprints into named functional groups.

Attempt to highlight a net in the GUI when supported.

Move a footprint to an absolute location.

Move capacitor footprints into a tight row near a target IC footprint.

Evaluate whether footprint placement is overlap-free and inside the board frame.

Return a structured placement-quality report for capable MCP clients.

Evaluate whether the PCB is physically clean enough to proceed.

Refill all copper zones.

Save the active board.

Score PCB placement quality and explain both hard failures and softer warnings.

Draw a rectangular board outline on Edge.Cuts.

Write board-level manufacturing constraints into the active .kicad_dru file.

Set the footprint copper side.

Add a rectangular PCB keepout / rule area to the active board.

Assign a net class when the runtime supports it.

Set the active board stackup using a file-backed profile.

Sync missing PCB footprints from schematic footprint assignments.

This is a file-based operation intended for initial board bring-up. It adds missing footprint instances to the .kicad_pcb file using schematic references, values, rotations, and assigned Library:Footprint names. When replace_mismatched=True, existing footprints with the same reference but the wrong footprint name are replaced in place.

Evaluate whether named schematic pad nets transferred cleanly onto PCB pads.

Estimate DC voltage drop and trace resistance.

Check whether the routed copper for a net looks sufficient for the load current.

Generate a rectangular copper plane on the requested copper layer.

Recommend local and bulk decoupling from a simple PDN heuristic.

Run the project quality gate and automatically apply server-side fixes.

Each iteration:

1. Evaluates all project quality gates.

2. For auto-applicable gates (annotation, zone refill) — calls the underlying fix implementation directly on the server, then re-evaluates.

3. For gates requiring agent action — returns the tool name and description so the agent can call it, then the agent must call this tool again to continue.

The loop runs up to max_iterations times applying auto-fixes. It stops early when all gates pass or when no further auto-fix is possible without agent involvement.

Args: max_iterations: Maximum number of auto-fix + re-evaluate cycles to attempt before returning control to the agent (1–20).

Generate a comprehensive design-status report.

Combines intent summary, v2 spec richness, project gate evaluation, and a prioritised list of next steps into a single structured report. This is the recommended first call after opening a project to understand its current state.

Show the persisted project design intent used by placement and release gates.

Return the resolved project design spec with explicit and inferred fields.

Return the next high-priority action derived from the current project gate.

Infer a design spec from the active PCB without writing it to disk.

Run the full project quality gate across schematic, PCB, DFM, and parity checks.

Return the full project gate in structured form for capable MCP clients.

Store high-level design intent used by placement, routing, and release-quality gates.

v1 parameters (all boards): connector_refs, decoupling_pairs, critical_nets, power_tree_refs, analog_refs, digital_refs, sensor_cluster_refs, rf_keepout_regions, manufacturer, manufacturer_tier.

v2 parameters (professional projects): power_rails (list of PowerRailSpec dicts), interfaces (list of InterfaceSpec dicts), mechanical (MechanicalConstraint dict), compliance (list of ComplianceTarget dicts), cost (CostTarget dict), thermal (ThermalEnvelope dict).

Validate the resolved design spec against the active project PCB.

Assign a named tuning profile to a net or wildcard net group.

Run FreeRouting on a Specctra DSN file and stage the resulting SES session.

Create or update a KiCad 10-style time-domain tuning profile.

Write differential-pair routing constraints for a pair of nets.

Stage a Specctra DSN file for FreeRouting.

Create a simple orthogonal route between two pads.

Stage a Specctra SES file and explain the KiCad import step.

List configured time-domain tuning profiles.

Write net-class routing constraints into the active .kicad_dru file.

Route a single straight track segment.

Write a length-tuning rule and report the current delta for a net.

Create a KiCad 10-inspired time-domain tuning rule with a length fallback.

Run PCB design rule checks.

Run schematic electrical rule checks.

Add a schematic bus, snapping endpoints to the 2.54 mm grid by default.

Add a bus wire entry marker, snapping its anchor to the 2.54 mm grid by default.

Add a global label, preserving the requested shape and rotation.

Add a hierarchical label, preserving the requested shape and rotation.

Add a jumper symbol to the schematic.

Add a schematic label, snapping its anchor to the 2.54 mm grid by default.

Add a no-connect marker, snapping it to the 2.54 mm grid by default.

Add a power symbol, snapping its anchor to the 2.54 mm grid by default.

Add a schematic symbol at an absolute coordinate.

Coordinates snap to the 2.54 mm schematic grid by default; set snap_to_grid=False only when an exact off-grid coordinate is intentional.

Add a schematic wire, snapping endpoints to the 2.54 mm grid by default.

Preview how netlist-aware schematic compilation will resolve endpoints and wires.

Renumber schematic references sequentially.

Place schematic symbols into semantically meaningful zones on the sheet.

Unlike the basic sch_auto_place_symbols which uses a plain grid, this tool categorises each symbol by its function (MCU, connector, power IC, sensor, passive, protection …) and places it in the corresponding region of the schematic sheet. The result is a readable, professionally structured schematic with logical signal flow (connectors on the left, processing in the centre, power/decoupling at the bottom).

Zone layout (column × row, each cell = 25.4 × 17.78 mm)::

Col →    0-2          3-5          6-8
Row 0:   connectors   MCU          UI/LED/SW
Row 3:   power IC     sensors/IC   protection
Row 5:   power_pass   passives     transistors/filter
Row 7:   test points  ---          misc

The actual sheet size is read from the schematic file. If the symbol count would overflow the current sheet, a warning is appended recommending sch_auto_resize_sheet to switch to a larger format (A3, A2, …) before re-running this tool.

Symbols already placed (not in symbol_list) are treated as fixed obstacles and will not be overwritten. Within each zone, symbols are arranged in a compact row-major sub-grid.

Args: symbol_list: Optional list of reference designators to place. If omitted, all symbols in the schematic are placed.

Returns: A summary showing how many symbols were placed per functional zone, plus an overflow warning if the sheet is too small.

Auto-place selected references using deterministic cluster, linear, or star layouts.

Unlike the legacy behaviour, this version reads all already-placed symbols first and avoids placing new symbols on top of them. Fixed/already-placed symbols that are not in symbol_list are treated as immovable obstacles.

Automatically grow the sheet to fit all currently placed symbols.

Reads the bounding box of all placed symbols and selects the smallest standard paper size (A4 → A3 → A2 → A1) that contains them with the configured margin. If the current sheet already fits, reports that no change is needed.

Returns: The chosen paper size and new dimensions, or a message if the current size is already sufficient.

Build (overwrite) the active schematic from structured symbol, wire, and label inputs.

IMPORTANT: This tool replaces the entire schematic content. Any symbols already placed in the schematic will be lost. To add symbols to an existing schematic without erasing it use sch_add_symbol / sch_add_wire / sch_add_label instead.

Coordinates are snapped to the 2.54 mm grid by default. When no coordinates are provided for a symbol, set auto_layout=True so the placement engine assigns non-overlapping positions automatically. If nets are also provided the layout is connection-aware and generates Manhattan wire segments from symbol pins. Nets that cannot resolve to at least two routable endpoints raise a clear error instead of silently producing a disconnected schematic.

Recommended workflow:

1. Call sch_find_free_placement(count=N) to obtain safe coordinates.

2. Pass those coordinates in the symbols list.

3. OR set auto_layout=True and omit coordinates entirely.

Check whether common power nets appear to be flagged.

Create a child schematic sheet and add it to the active top-level schematic.

Remove a placed symbol and any directly attached wire segments.

Remove a specific wire segment using its UUID or unique UUID prefix.

Evaluate whether schematic structure and hierarchy look electrically meaningful.

Evaluate whether the schematic is clean enough to proceed.

Find N collision-free placement coordinates for new symbols.

Reads the current schematic, builds an occupancy grid from all existing symbols, and returns count coordinate pairs that do not overlap with any placed symbol. Call this before sch_add_symbol to get safe (x, y) values.

Args: count: Number of free coordinate slots to return (default 1, max 64). cell_width_mm: Grid cell width in mm (default 25.4 — one 10-mil grid unit). cell_height_mm: Grid cell height in mm (default 17.78).

Returns: A list of (x_mm, y_mm) coordinate pairs, one per requested slot.

Return the estimated bounding box of every symbol in the active schematic.

Use this before calling sch_add_symbol or sch_build_circuit to understand which areas of the schematic sheet are already occupied. The bounding boxes are heuristic estimates (KiCad does not expose exact extents via the file API) but are conservative enough to avoid overlap in practice.

Returns: A table of all symbols with their centre position and estimated bounding-box corners (x_min, y_min, x_max, y_max) in mm, plus an occupied-area summary.

Summarize the active schematic as a textual net connectivity graph.

List all labels in the schematic.

List unique net names derived from labels.

Calculate absolute pin positions for a given symbol placement.

Return metadata for a specific child sheet.

List all schematic symbols.

Return full details for a subcircuit template.

Args: template_name: Template name as returned by sch_list_templates() (e.g. "buck_converter_generic").

Returns: Structured template description including parameters, symbols, nets, and placement hints.

List all wires in the schematic.

Instantiate a subcircuit template — returns a structured action plan.

This tool returns a structured plan describing the symbols, connections, and part-search steps needed to add the subcircuit to the schematic. It does NOT directly edit the schematic (use the plan as a guide for calling sch_add_symbol, sch_add_wire, lib_recommend_part, etc.).

Args: template_name: Template name (from sch_list_templates()). prefix: Reference prefix applied to all template refs (e.g. "PWR_" produces PWR_U1, PWR_L1, etc.). params: Dict of parameter overrides (e.g. {"vout_v": 5.0}).

Returns: Step-by-step instantiation plan in markdown format.

List child sheets from the active top-level schematic.

List candidate pins and units that can participate in a swap workflow.

List all available reference subcircuit templates.

Templates are pre-wired subcircuit blueprints for common building blocks (buck converter, LDO, USB Type-C, MCU decoupling, Ethernet with magnetics).

Call sch_get_template_info() for full parameter and placement details, then sch_instantiate_template() to add the subcircuit to the schematic.

Move an existing symbol instance to a new absolute coordinate.

Ask KiCad to reload the active schematic.

Route deterministic Manhattan wire segments between two placed symbol pins.

Change the schematic sheet (paper) size.

Use this when the current sheet is too small to fit all symbols — for example after sch_auto_place_functional warns that symbols were placed outside the sheet boundary, or when you receive a screenshot showing components outside the red sheet border.

Supported sizes (landscape): A4, A3, A2, A1, A0, A (letter), B, C, D, E, USLetter, USLegal.

After resizing you should call sch_auto_place_functional again so that symbols are re-distributed across the larger sheet.

Args: paper: Target paper size keyword (default "A3").

Returns: Confirmation with old and new dimensions.

Record a gate-swap back-annotation intent for a multi-unit component.

Record a pin-swap back-annotation intent for a component.

Trace a named net through the active schematic and matching child sheets.

Update a property on a placed symbol.

Map interface specs from the project design intent to KiCad net classes.

For each interface with an impedance target, this tool generates the pcb_set_net_class() calls needed to enforce clearance and diff-pair rules. When dry_run=True (default), only returns the plan without executing it.

Args: interfaces: List of InterfaceSpec dicts from project_get_design_spec(). dry_run: If True, return the mapping plan without modifying the project. Set to False to have the tool call pcb_set_net_class() for each class.

Returns: Net class plan or confirmation of changes applied.

Estimate decoupling placement quality around an IC power pin.

Estimate PCB trace impedance using quasi-static interconnect formulas.

Solve for a trace width that meets the requested impedance target.

Estimate differential-pair length skew and delay mismatch from board tracks.

Estimate via-stub resonance and risk for selected vias on the active board.

Generate a practical board stackup recommendation and target trace geometry.

List all built-in dielectric materials with Er, loss tangent, and frequency range.

Use the returned material keys with si_synthesize_stackup_for_interfaces() to select the appropriate laminate for your design.

Persist a SPICE directive used by future MCP simulation runs.

Estimate loop crossover and phase margin from an AC sweep.

Run a small-signal AC sweep.

Run a DC sweep for an independent source.

Run a DC operating-point analysis.

Run a transient time-domain simulation.

Synthesise a PCB stackup that meets the impedance requirements of the given interfaces.

Analyses each InterfaceSpec dict and recommends:

• Layer count

• Dielectric material

• Copper weight per layer

• Outer dielectric thickness for target impedance

• Net class settings (impedance, clearance, diff-pair gap)

Args: interfaces: List of InterfaceSpec dicts (matching project_set_design_intent interface format). Each must have at least kind and optionally impedance_target_ohm, differential, diff_skew_max_ps. cost_tier: "standard" (FR4), "midloss" (FR4 mid/low-loss), "highspeed" (Rogers/Megtron). Overrides material selection. board_thickness_mm: Target board thickness in mm (1.0, 1.6, 2.0, 3.2).

Returns: Recommended stackup specification and net class table in human-readable markdown, ready to pass to pcb_set_stackup() and pcb_set_net_class().

Validate that each net group is matched within the supplied tolerance.

Update the active IDE context pushed by KiCad Studio.

Estimate how many stitched thermal vias are needed for the target resistance.

Check whether the board already has copper pour support for the net.

Write matched-length rules for both nets in a differential pair.

Backward-compatible alias for route_tune_length().

Run DRC and ERC and summarize readiness.

Compare PCB footprint references against the schematic symbol references.

Create a new design variant, optionally cloning an existing variant.

Diff the effective BOM between two design variants.

Export a variant-specific BOM into the project output directory.

List available design variants and basic component counts.

Set the active design variant for the current project.

Override component population, value, or footprint in a variant.

Commit the current project state as a named checkpoint.

Show the current project diff versus a checkpoint commit.

Initialize a Git repository for the KiCad project directory.

List checkpoint commits created by the MCP tool.

Restore project files from a previous checkpoint commit.