project_set_design_intent
Define high-level design intent to guide PCB placement, routing, and release-quality gates. Capture constraints for power, interfaces, compliance, and thermal.
Instructions
Store high-level design intent used by placement, routing, and release-quality gates.
v1 parameters (all boards): connector_refs, decoupling_pairs, critical_nets, power_tree_refs, analog_refs, digital_refs, sensor_cluster_refs, rf_keepout_regions, manufacturer, manufacturer_tier.
v2 parameters (professional projects): power_rails (list of PowerRailSpec dicts), interfaces (list of InterfaceSpec dicts), mechanical (MechanicalConstraint dict), compliance (list of ComplianceTarget dicts), cost (CostTarget dict), thermal (ThermalEnvelope dict).
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cost | No | ||
| thermal | No | ||
| compliance | No | ||
| interfaces | No | ||
| mechanical | No | ||
| analog_refs | No | ||
| power_rails | No | ||
| digital_refs | No | ||
| manufacturer | No | ||
| critical_nets | No | ||
| connector_refs | No | ||
| power_tree_refs | No | ||
| decoupling_pairs | No | ||
| manufacturer_tier | No | ||
| rf_keepout_regions | No | ||
| sensor_cluster_refs | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |