List all available tool categories and capabilities.

Get the tool names available in a specific category.

Set the active KiCad project directory and file paths.

Show the currently configured KiCad project paths.

Store high-level design intent used by placement, routing, and release-quality gates.

v1 parameters (all boards): connector_refs, decoupling_pairs, critical_nets, power_tree_refs, analog_refs, digital_refs, sensor_cluster_refs, rf_keepout_regions, manufacturer, manufacturer_tier.

v2 parameters (professional projects): power_rails (list of PowerRailSpec dicts), interfaces (list of InterfaceSpec dicts), mechanical (MechanicalConstraint dict), compliance (list of ComplianceTarget dicts), cost (CostTarget dict), thermal (ThermalEnvelope dict).

Show the persisted project design intent used by placement and release gates.

Return the resolved project design spec with explicit and inferred fields.

Infer a design spec from the active PCB without writing it to disk.

Validate the resolved design spec against the active project PCB.

Return the next high-priority action derived from the current project gate.

Run the project quality gate and automatically apply server-side fixes.

Each iteration:

1. Evaluates all project quality gates.

2. For auto-applicable gates (annotation, zone refill) — calls the underlying fix implementation directly on the server, then re-evaluates.

3. For gates requiring agent action — returns the tool name and description so the agent can call it, then the agent must call this tool again to continue.

The loop runs up to max_iterations times applying auto-fixes. It stops early when all gates pass or when no further auto-fix is possible without agent involvement.

Args: max_iterations: Maximum number of auto-fix + re-evaluate cycles to attempt before returning control to the agent (1–20).

Generate a comprehensive design-status report.

Combines intent summary, v2 spec richness, project gate evaluation, and a prioritised list of next steps into a single structured report. This is the recommended first call after opening a project to understand its current state.

List recently opened KiCad projects from KiCad's config files.

Scan a directory and report any KiCad project files it contains.

Create a new minimal KiCad project structure and activate it.

Get KiCad version information and current connection status.

Show a concise startup guide and all tool categories.

Summarize the current board.

List board tracks.

List board vias.

List board footprints.

List every layer referenced by a footprint block, including inner layers.

List all board nets.

List all board copper zones.

List graphical board shapes.

List board pads.

List enabled board layers.

Show the current stackup.

Set the active board stackup using a file-backed profile.

Estimate trace impedance for the supplied width on the named stackup layer.

Run a heuristic creepage clearance review against pad spacing.

List currently selected items in the PCB editor.

Return the current board as a bounded S-expression string.

Report currently unconnected board items using the latest DRC view.

Read the active board design rules file when available.

Write board-level manufacturing constraints into the active .kicad_dru file.

Add a single track segment.

Add multiple tracks in a single operation.

Add a via.

Add a blind or buried via between the requested copper layers.

Add a microvia between adjacent copper layers.

Add a board graphic segment.

Add a board graphic circle.

Add a board graphic rectangle.

Draw a rectangular board outline on Edge.Cuts.

Add board text.

Add a production barcode marker to the board file.

Delete items by UUID.

Save the active board.

Refill all copper zones.

Attempt to highlight a net in the GUI when supported.

Assign a net class when the runtime supports it.

Move a footprint to an absolute location.

Set the footprint copper side.

Inject an inner-layer graphic primitive into a footprint block.

Sync missing PCB footprints from schematic footprint assignments.

This is a file-based operation intended for initial board bring-up. It adds missing footprint instances to the .kicad_pcb file using schematic references, values, rotations, and assigned Library:Footprint names. When replace_mismatched=True, existing footprints with the same reference but the wrong footprint name are replaced in place.

Place PCB footprints from the current schematic using deterministic heuristics.

Move capacitor footprints into a tight row near a target IC footprint.

Cluster existing footprints into named functional groups.

Arrange selected footprints into a straight row or column.

Add a copper zone with an arbitrary polygon outline on one copper layer.

Backward-compatible alias for pcb_add_zone().

Add a rectangular PCB keepout / rule area to the active board.

Append standard mounting-hole footprints around the current board frame.

Append simple fiducial footprints near the board corners.

List stored PCB design blocks created from selected footprints.

Capture a reusable PCB design block from selected footprint references.

Place a stored PCB design block by cloning its saved footprint blocks.

Create small copper helper zones at simple pad-to-track junctions.

Run a force-directed spring-embedder placement algorithm on a set of components.

This tool computes optimised X/Y positions for components based on their net connectivity without requiring KiCad to be open. Use it to get a placement suggestion, then apply the result with pcb_move_footprint for each component.

Args: component_positions: List of component dicts with keys: ref (str), x (float, mm), y (float, mm), w (float, mm, optional default 2), h (float, mm, optional default 2), fixed (bool, optional default false). nets: List of net dicts with keys: name (str), refs (list[str]), weight (float, optional default 1.0). board_width_mm: Soft boundary width in mm (default 100). board_height_mm: Soft boundary height in mm (default 80). iterations: Number of spring-embedder iterations (default 300). k_spring: Spring attraction coefficient (default 0.4). k_repel: Coulomb repulsion coefficient (default 80.0).

Returns: JSON string with optimised positions for each component.

Generate a BGA fanout via-placement plan (dog-ear or inline strategy).

Returns per-ball via coordinates and suggested track widths so the agent can call pcb_add_via and pcb_add_track to physically fanout the BGA. Actual pad coordinates must come from the board footprint (use pcb_get_pads).

Args: balls: List of ball dicts with keys: row (str, e.g. "A"), col (int, 1-based), net (str), x_mm (float, ball centre X), y_mm (float, ball centre Y). pitch_mm: Ball pitch in mm (e.g. 0.5, 0.65, 0.8, 1.0). via_drill_mm: Via drill diameter in mm (default 0.2). via_annular_mm: Via annular ring width in mm (default 0.1). escape_layer: Inner copper layer to fan out to (default "In1.Cu"). strategy: "dog_ear" (diagonal escape, most common) or "inline" (horizontal escape, for large pitch).

Returns: JSON string with via placement plan for each ball.

List all schematic symbols.

List all wires in the schematic.

List all labels in the schematic.

List unique net names derived from labels.

Add a schematic symbol at an absolute coordinate.

Coordinates snap to the 2.54 mm schematic grid by default; set snap_to_grid=False only when an exact off-grid coordinate is intentional.

Add a schematic wire, snapping endpoints to the 2.54 mm grid by default.

Add a schematic label, snapping its anchor to the 2.54 mm grid by default.

Add a power symbol, snapping its anchor to the 2.54 mm grid by default.

Add a schematic bus, snapping endpoints to the 2.54 mm grid by default.

Add a bus wire entry marker, snapping its anchor to the 2.54 mm grid by default.

Add a no-connect marker, snapping it to the 2.54 mm grid by default.

List candidate pins and units that can participate in a swap workflow.

Record a pin-swap back-annotation intent for a component.

Record a gate-swap back-annotation intent for a multi-unit component.

Add a jumper symbol to the schematic.

Update a property on a placed symbol.

Move an existing symbol instance to a new absolute coordinate.

Remove a specific wire segment using its UUID or unique UUID prefix.

Remove a placed symbol and any directly attached wire segments.

Preview how netlist-aware schematic compilation will resolve endpoints and wires.

Build (overwrite) the active schematic from structured symbol, wire, and label inputs.

IMPORTANT: This tool replaces the entire schematic content. Any symbols already placed in the schematic will be lost. To add symbols to an existing schematic without erasing it use sch_add_symbol / sch_add_wire / sch_add_label instead.

Coordinates are snapped to the 2.54 mm grid by default. When no coordinates are provided for a symbol, set auto_layout=True so the placement engine assigns non-overlapping positions automatically. If nets are also provided the layout is connection-aware and generates Manhattan wire segments from symbol pins. Nets that cannot resolve to at least two routable endpoints raise a clear error instead of silently producing a disconnected schematic.

Recommended workflow:

1. Call sch_find_free_placement(count=N) to obtain safe coordinates.

2. Pass those coordinates in the symbols list.

3. OR set auto_layout=True and omit coordinates entirely.

Calculate absolute pin positions for a given symbol placement.

Check whether common power nets appear to be flagged.

Renumber schematic references sequentially.

Ask KiCad to reload the active schematic.

Create a child schematic sheet and add it to the active top-level schematic.

Add a hierarchical label, preserving the requested shape and rotation.

Add a global label, preserving the requested shape and rotation.

List child sheets from the active top-level schematic.