write_rtl
Write or replace complete HDL source and documentation files using full UTF-8 content for Amaranth, MyHDL, Verilog, or docs; Python files receive a syntax check, and tests use write_test.
Instructions
Write a design source file or a doc, replacing the whole file. Always send the full new content: diffs and patches are not accepted. Allowed paths: hdl//*.py for Amaranth and MyHDL projects (the entry file is hdl/.py); src/.v for Verilog projects; docs//*.md (except the generated docs/verification.md). Tests go through write_test instead. Content must be UTF-8 text of at most 256 KiB. A .py file gets a syntax check (it is never run); the file is saved even when the check fails, and then ok is false with file:line:col and the message.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"project": "<project>",
"path": "<path>",
"content": "<content>"
},
"name": "write_rtl"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | ||
| content | Yes | ||
| project | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| details | No | ||
| summary | Yes | ||
| artifacts | No | ||
| next_hints | No |