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emit_verilog

Destructive

Generate a Verilog core from Amaranth, MyHDL, or Verilog project code, validate ports against Tiny Tapeout pins, regenerate the wrapper, and lint with Verilator and Yosys.

Instructions

Turn the project's design into Verilog and check it. For Amaranth and MyHDL this runs your hdl/.py in a container and writes the generated core to src/.v; a Verilog project's src/.v is used as it is. The tool then checks the core's ports against the Tiny Tapeout pins (names, directions, widths), regenerates the tt_um_ wrapper in src/project.v, and lints everything with Verilator (-Wall; latches are errors) and Yosys check -assert (multiple drivers and logic loops are errors). ok is false for a Python error (with file and line), bad ports, or any lint finding; details.lint lists {severity, code, file, line, col, msg}. Takes a few seconds to a minute; the first call is the slowest.

Tool call template

Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.

{
  "id": 1,
  "jsonrpc": "2.0",
  "method": "tools/call",
  "params": {
    "arguments": {
      "project": "<project>"
    },
    "name": "emit_verilog"
  }
}

Input Schema

Name	Required	Description	Default
`project`	Yes

Output Schema

Name	Required	Description	Default
`ok`	Yes
`details`	No
`summary`	Yes
`artifacts`	No
`next_hints`	No

Schema Changelog

Changes observed during successful MCP inspections.

First observedv0.1.0Nov 14, 2026

TDQS

A4/5.0

Behavior4/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

Annotations flag destructiveHint=true and the description substantiates that: it writes/overwrites src/<name>.v and regenerates src/project.v, and reports failure modes (Python errors with file and line, bad ports, lint findings). It also discloses runtime ('a few seconds to a minute; the first call is the slowest'). A brief note on whether existing files are overwritten without confirmation would push this higher, but the behavioral disclosure is strong and consistent with the annotations.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness4/5

Is the description appropriately sized, front-loaded, and free of redundancy?

Dense but front-loaded: the core action is stated first, then mechanics, then failure semantics and timing. It is longer than typical but nearly every sentence carries information an agent needs; only the port-check and lint detail could be slightly tightened.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness5/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

For a mutating build/lint tool with an output schema available, the description covers inputs' effects, side effects on the filesystem, failure semantics, the shape of details.lint, and timing expectations. Nothing an agent needs to invoke it correctly appears to be missing.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema coverage is 0% for the single 'project' parameter, so the description must carry the meaning. It does so indirectly by showing that <name> maps to hdl/<name>.py and src/<name>.v, implying the parameter is the project name used to locate those files, but it never states this explicitly or gives format/validity constraints.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

Opens with a specific verb+resource: 'Turn the project's design into Verilog and check it.' It goes on to name the concrete artifacts (src/<name>.v, tt_um_<name> wrapper) and the checks performed, which clearly separates it from siblings like write_rtl or synthesize.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines3/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description explains the conditional paths (Amaranth/MyHDL generates, a Verilog project's src file is used as-is), which implies when this tool applies. However, it never explicitly states when to prefer it over synthesize or run_tests, nor any prerequisites such as required project state, so usage is only implied.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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