synthesize
Convert RTL into sky130 logic gates, catch lint issues, and report cell count, area, and estimated tile utilization to confirm the design fits.
Instructions
Turn the design into real chip gates and say how big it is. Synthesis is the step where a program (Yosys) replaces your RTL with the small ready-made logic gates and flip-flops of the sky130 chip library, the same way Tiny Tapeout's own flow does. The tool first runs the same checks as emit_verilog (a lint problem stops it, with file and line), then synthesizes with the clock from spec.yaml recorded as Tiny Tapeout does (this recipe optimizes for small area, so the clock does not change the gates; timing is checked at layout). The summary gives the number of cells (flip-flops, which store bits, and logic gates), the total cell area in um^2, the most used cell types, and the estimated utilization: how much of your tile's usable area the cells would fill. Utilization is an ESTIMATE; real placement (layout, milestone M2) gives the real number, and it needs headroom (above 90% is risky, above 100% will not fit). The tile size comes from tiles in spec.yaml (default 1x1); a design far too big for it is stopped early with a "too big" message and what to do: make the design smaller, or ask the owner about a bigger tile (it costs money, so the owner decides). ok is false for a lint or Yosys error, a combinational loop, a signal driven twice, an undriven output, a cell that Tiny Tapeout does not allow, a design that is too big, or a time-out (900 s). A latch you wrote on purpose (always_latch) is reported as a warning with file and line. A clock above 66 MHz also warns: Tiny Tapeout's pins cannot go that fast. The netlist is saved in build/synth/ (a convenience copy of the latest run that wrote one; the ledger's netlist_sha256 records what was synthesized). Usually takes seconds to a minute.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"project": "<project>"
},
"name": "synthesize"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| project | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| details | No | ||
| summary | Yes | ||
| artifacts | No | ||
| next_hints | No |