run_tests
Simulate your design's cocotb tests on Icarus Verilog or Verilator, with an optional gate-level netlist run, to confirm tests pass and report the first failing assertion with file:line.
Instructions
Run the project's cocotb tests (every test/test*.py) against the design on Icarus Verilog or Verilator. It first does what emit_verilog does (elaborate, check ports, regenerate the wrapper, lint); only if that is ok does it simulate the Tiny Tapeout testbench test/tb.v. ok is true only if at least one test ran (skipped tests do not count) and none failed. The summary names the first failing test, its file:line, the assertion, and expected vs actual. test_filter is a regex that cocotb searches in '.' (for example 'test.test_wraps_at_255$'); a filtered run never counts as a full run. waves=True keeps a wave file under build/waves/ for inspect_waves. details.tests lists every test with outcome and the requirement ids it covers; details.coverage says which spec.yaml requirements have a passing test. The first Verilator run takes about half a minute; later runs reuse the build.
gl=True runs the tests at gate level (Icarus only; with Verilator it is an error). The tool first does what synthesize does, with the same checks and the same time limits (a design that fails stops there, and so does one far over the size budget; the summary says gate-level simulation could not run. A design only slightly too big is simulated, with a note), then runs the SAME test files on the resulting sky130 netlist, with the cell models of the chip library (a netlist has no RTL names: a test may only use the pins of tb, such as uo_out, and not internal signals). This catches what RTL simulation cannot: logic that behaves differently once it is real gates, such as a missing reset or an uninitialized flip-flop. The summary's first line says "Gate-level simulation" so it is never mistaken for an RTL run. A gate-level run never changes the RTL results or the RTL wave files: its waves are kept apart in build/waves/icarus-gl/ (inspect_waves reads them). It can take up to 25 minutes in the worst case; a small design takes seconds to a minute. details.gl holds the netlist hash.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"project": "<project>",
"simulator": "<simulator>"
},
"name": "run_tests"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| gl | No | ||
| waves | No | ||
| project | Yes | ||
| simulator | Yes | ||
| test_filter | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ok | Yes | ||
| details | No | ||
| summary | Yes | ||
| artifacts | No | ||
| next_hints | No |