A
licenseB
qualityB
maintenanceEnables AI agents to perform high-level HDL workflows including linting, simulation, synthesis, formal verification, FPGA bitstream builds, and waveform or netlist inspection over OSS CAD Suite tools.
15
MIT
siliconsmith-mcp
by RFingAdam
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TDQS
A4.2/5.0
Scored across 13 tools
Disambiguation4/5
Most tools target a clearly distinct stage of the chip design loop (spec, RTL, emit, sim, synth, waves, status) and the write_* family is separated by file kind. The main soft spots are emit_verilog vs. synthesize (both run the same lint/check pass) and run_tests(gl=True) vs. synthesize (the gate-level path re-runs synthesis), though the descriptions explicitly clarify the boundaries.
Naming Consistency4/5
The dominant pattern is verb_noun (create_project, list_files, read_file, write_rtl, write_test, write_spec, emit_verilog, run_tests, inspect_waves), which is predictable. The deviations are bare single words (synthesize, status, explain, toolchain_info) — still unambiguous but not a uniform pattern.
Tool Count5/5
13 tools is comfortably in the well-scoped range, and each maps to a real step (scaffold, edit, verify, synthesize, simulate, inspect, report). No obvious filler or redundant duplicates.
Completeness4/5
The full design loop is covered: project creation, file read/write, spec validation, Verilog emission and lint, RTL and gate-level simulation, synthesis sizing, wave inspection, and a status/coverage ledger. Minor gaps exist — no delete/rename/move file operation, no build-artifact listing without a flag, and spec approval and layout/PnR are intentionally outside the tool surface.
Maintenance
ActivityMaintained
ResponsivenessNo recent community issues