yosys_synthesize
Synthesize Verilog/SystemVerilog designs with Yosys targeting generic, iCE40, or Sky130, returning cell counts and warnings to catch synthesis hazards before physical design.
Instructions
Synthesizes a Verilog/SystemVerilog design using Yosys, mapping to generic gates, iCE40 FPGA, or Sky130 standard cells, and returns structured cell counts and warnings.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Working directory where source files reside. | |
| target | No | Target architecture/library (default: 'generic'). | |
| flatten | No | Whether to flatten the design hierarchy during synthesis. | |
| timeout_ms | No | Maximum synthesis timeout in milliseconds (default: 30000). | |
| top_module | Yes | Name of the top-level module to synthesize. | |
| output_netlist | No | Optional output Verilog netlist file path. | |
| verilog_sources | Yes | List of Verilog/SystemVerilog source files. |