yosys_hierarchy
Inspect Verilog module hierarchy to identify instantiated submodules and flag missing or unresolved blackboxes before synthesis.
Instructions
Inspects module hierarchy, detecting instantiated submodules and flagging missing/unresolved blackboxes.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Working directory where source files reside. | |
| timeout_ms | No | Timeout in milliseconds (default: 20000). | |
| top_module | Yes | Name of the top-level module. | |
| verilog_sources | Yes | List of Verilog/SystemVerilog source files. |