yosys_check_latch
Detect synthesis hazards like inferred latches and combinational loops by elaborating RTL and pinpointing exact source lines.
Instructions
Performs fast RTL elaboration and latch checking to identify inferred transparent latches, combinational loops, and multiple drivers with exact source lines.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Working directory where source files reside. | |
| timeout_ms | No | Timeout in milliseconds (default: 20000). | |
| top_module | Yes | Name of the top-level module to inspect. | |
| verilog_sources | Yes | List of Verilog/SystemVerilog source files. |