rtl_review
Run a static AST-backed audit of Verilog/SystemVerilog code to detect assignment, reset, bitwidth, and undriven-net issues, then compute a 0–100 quality score and return actionable fixes.
Instructions
Performs full AST-backed static RTL review and semantic code audit on Verilog/SystemVerilog designs, evaluating assignment discipline, reset polarity, bitwidths, undriven nets, and computing a 0–100 quality score with actionable fix suggestions.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory where source files reside. | |
| ruleset | No | Rule severity enforcement level (default: standard). | |
| top_module | No | Top module name for AST hierarchy analysis. | |
| include_info | No | Whether to include info-level violations (e.g. unused signals). | |
| verilog_sources | Yes | List of Verilog/SystemVerilog source files to review. |