rtl_check_widths
Analyze Verilog/SystemVerilog designs for bitwidth mismatches, catching implicit truncation and bit expansion errors to prevent data loss and unintended behavior.
Instructions
Performs semantic bitwidth analysis on Verilog/SystemVerilog designs, detecting implicit truncation and bit expansion mismatches.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory where source files reside. | |
| top_module | No | Top module name for hierarchy analysis. | |
| verilog_sources | Yes | List of Verilog/SystemVerilog source files to check. |