rtl_check_assignments
Audit Verilog/SystemVerilog files to detect blocking assignments in sequential blocks and non-blocking assignments in combinational blocks, ensuring correct RTL coding discipline.
Instructions
Audits Verilog/SystemVerilog source files specifically for assignment discipline violations: blocking '=' in sequential clocked blocks, or non-blocking '<=' in combinational blocks.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"verilog_sources": "<verilog_sources>"
},
"name": "rtl_check_assignments"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory where source files reside. | |
| top_module | No | Top module name for AST hierarchy analysis. | |
| verilog_sources | Yes | List of Verilog/SystemVerilog source files to audit. |