fpga_synth
Synthesizes Verilog RTL into a nextpnr-compatible JSON netlist for iCE40 or ECP5 FPGAs, reporting cell and wire counts to enable subsequent placement and routing.
Instructions
Synthesizes RTL to a nextpnr-ready JSON netlist with Yosys (synth_ice40/synth_ecp5), returning cell and wire counts. First stage of the FPGA flow; feed jsonNetlist into fpga_place_route.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory. | |
| family | No | FPGA family (default: ice40). | |
| top_module | Yes | Top module name. | |
| verilog_sources | Yes | RTL source files. |