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zesun33
by zesun33

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    • A
      license
      A
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      D
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      Provides AI assistants with a complete FPGA toolchain for HDL linting, simulation, synthesis, and place-and-route across various hardware targets. It features a GitHub-backed IP core registry that enables users to search for and import MIT-licensed cores directly through their chat interface.
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    • A
      license
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      D
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      Enables AI assistants to drive Xilinx Vivado, Intel Quartus, and Anlogic TangDynasty for FPGA development, including project creation, synthesis, implementation, timing closure, and hardware programming through natural language.
      27 PyPI
      3
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    • A
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      A
      quality
      B
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      Enables AI coding agents and IDEs to synthesize Verilog/SystemVerilog designs with Yosys, inspect cell hierarchies and gate counts, and detect synthesis hazards like inferred latches and combinational loops before physical design flows.
      4
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    • A
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      A
      quality
      B
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      Enables AI coding agents and IDEs to execute ASIC physical design flows including floorplanning, placement, clock tree synthesis, routing, and static timing analysis through the OpenROAD engine, returning concise low-token JSON metrics.
      6
      5 npm
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    • A
      license
      Not graded
      quality
      C
      maintenance
      Enables AI coding assistants to drive Xilinx Vivado through natural language, letting users open .xpr projects, run synthesis, implementation, and bitstream generation, inspect timing, resource, and clock reports, and launch simulations to read signal values or set breakpoints. It also exposes design hierarchy queries and arbitrary TCL execution, so FPGA design flows can be operated conversationally on Windows.
      MIT

    TDQS

    A4.2/5.0

    Scored across 6 tools

    Disambiguation5/5

    Each tool has a unique, clearly defined role in the FPGA workflow (synthesis, place-and-route, bitstream, programming, board listing, toolchain info). No overlap or ambiguity.

    Naming Consistency5/5

    All tools follow a consistent 'fpga_' prefix with descriptive verb/noun combinations. The pattern is uniform and predictable.

    Tool Count5/5

    Six tools cover the essential FPGA flow without redundancy or unnecessary additions. The count fits the domain scope well.

    Completeness4/5

    The tool set covers the core synthesis-to-programming pipeline and auxiliary info/board queries. Slightly missing advanced features like device status or configuration readback, but the main workflow is fully supported.

    Maintenance

    ActivityMaintained
    ResponsivenessNo issues