Skip to main content
Glama
mcp-fpga
by zesun33

Related Servers

Alternatives to mcp-fpga

No user-submitted related servers found.

    Related Servers

    • A
      license
      A
      quality
      D
      maintenance
      Provides AI assistants with a complete FPGA toolchain for HDL linting, simulation, synthesis, and place-and-route across various hardware targets. It features a GitHub-backed IP core registry that enables users to search for and import MIT-licensed cores directly through their chat interface.
      15
      1
      MIT
    • A
      license
      Not graded
      quality
      C
      maintenance
      Enables AI assistants to drive Xilinx Vivado, Intel Quartus, and Anlogic TangDynasty for FPGA development, including project creation, synthesis, implementation, timing closure, and hardware programming through natural language.
      32 PyPI
      6
      MIT
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI coding agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado across the full FPGA flow, from GUI, headless Tcl, or attached sessions through synthesis, implementation, timing and CDC analysis, waveform queries, and device programming. It exposes 32 curated tools plus evidence-driven workflow prompts that return structured timing/IO reports, Chinese-language CRITICAL WARNING diagnostics, and guarded bitstream generation.
      -
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI coding agents to safely drive a locally installed Xilinx Vivado FPGA flow, covering session control, synthesis, implementation, timing and CDC analysis, XDC constraints, IP inspection, waveform queries, and device programming with structured, evidence-based diagnostics.
      -
    • A
      license
      A
      quality
      B
      maintenance
      Enables AI coding agents and IDEs to synthesize Verilog/SystemVerilog designs with Yosys, inspect cell hierarchies and gate counts, and detect synthesis hazards like inferred latches and combinational loops before physical design flows.
      4
      14 npm
      Apache 2.0
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI agents such as Claude Code, Cursor, and Codex to safely drive a locally installed Xilinx Vivado across the full FPGA flow, with tools for sessions, synthesis, implementation, timing, CDC, XDC, IP, waveform analysis, and device programming. It also provides evidence-driven workflow prompts, structured timing reports with baseline comparison, offline VCD queries, Chinese diagnostics for critical warnings, and environment self-check/repair.
      -

    TDQS

    A4.2/5.0

    Scored across 6 tools

    Disambiguation5/5

    Each tool has a unique, clearly defined role in the FPGA workflow (synthesis, place-and-route, bitstream, programming, board listing, toolchain info). No overlap or ambiguity.

    Naming Consistency5/5

    All tools follow a consistent 'fpga_' prefix with descriptive verb/noun combinations. The pattern is uniform and predictable.

    Tool Count5/5

    Six tools cover the essential FPGA flow without redundancy or unnecessary additions. The count fits the domain scope well.

    Completeness4/5

    The tool set covers the core synthesis-to-programming pipeline and auxiliary info/board queries. Slightly missing advanced features like device status or configuration readback, but the main workflow is fully supported.