mcp-fpga
Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| MCP_FPGA_RUNTIME | No | Set to 'host' to force using host binaries instead of container execution. Default is container execution via Podman. |
Instructions
Guidance the server publishes about itself, which clients place ahead of the tool catalog so the model reads it before choosing anything.
This server publishes no instructions, or was last inspected before Glama recorded them.
Capabilities
Features and capabilities supported by this server
Protocol revision2025-11-25
| Capability | Details |
|---|---|
| tools | {} |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| fpga_synthA | Synthesizes RTL to a nextpnr-ready JSON netlist with Yosys (synth_ice40/synth_ecp5), returning cell and wire counts. First stage of the FPGA flow; feed jsonNetlist into fpga_place_route. |
| fpga_place_routeA | Runs nextpnr place-and-route for iCE40/ECP5 from a Yosys JSON netlist. Device and package resolve from an explicit pair or a board preset (explicit wins). Returns utilization and Fmax from the JSON report. Use fpga_boards to list presets. |
| fpga_bitstreamA | Packs a routed image to a bitstream: icepack (.asc to .bin) for iCE40, ecppack (optionally --compress) for ECP5. Feed the result into fpga_program. |
| fpga_programA | Flashes an iCE40 bitstream via iceprog. Dry-run (default) only reports the planned command: real flashing needs board hardware this host cannot verify. ECP5 needs openFPGALoader, which is absent from the image. |
| fpga_boardsA | Lists board presets (device, package, programmer) for place-and-route targeting. Use a preset name as fpga_place_route board input. |
| fpga_toolchain_infoA | Returns active container/host runtime and versions of Yosys, nextpnr, icepack, ecppack, and iceprog. |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |
TDQS
Scored across 6 tools
Each tool has a unique, clearly defined role in the FPGA workflow (synthesis, place-and-route, bitstream, programming, board listing, toolchain info). No overlap or ambiguity.
All tools follow a consistent 'fpga_' prefix with descriptive verb/noun combinations. The pattern is uniform and predictable.
Six tools cover the essential FPGA flow without redundancy or unnecessary additions. The count fits the domain scope well.
The tool set covers the core synthesis-to-programming pipeline and auxiliary info/board queries. Slightly missing advanced features like device status or configuration readback, but the main workflow is fully supported.