verilator_simulate
Run RTL simulations with automatic testbench generation when needed, enabling hardware verification of Verilog/SystemVerilog designs through configurable coverage, waveforms, and assertions.
Instructions
Run RTL simulation with automatic testbench generation if needed
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| design | Yes | Design file or compiled directory | |
| defines | No | Macro definitions | |
| timeout | No | Simulation timeout in milliseconds | |
| verbose | No | Verbose output | |
| plusargs | No | Plusargs to pass to simulation | |
| outputDir | No | Output directory for simulation artifacts | sim_output |
| testbench | No | Testbench file (will auto-generate if missing) | |
| topModule | No | Top module name | |
| waveformFile | No | Waveform output file | |
| coverageTypes | No | Coverage types to collect | |
| enableCoverage | No | Enable coverage collection | |
| enableWaveform | No | Generate waveform dump | |
| simulationTime | No | Override simulation time | |
| waveformFormat | No | Waveform format | vcd |
| enableAssertions | No | Enable assertion checking | |
| useExistingBuild | No | Use existing compiled output | |
| optimizationLevel | No | Optimization level | |
| autoGenerateTestbench | No | Auto-generate testbench if missing |