Verilator MCP Server
Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| LOG_LEVEL | No | Set logging level (debug, info, warn, error) | info |
| VERILATOR_PATH | No | Override Verilator installation path |
Instructions
Guidance the server publishes about itself, which clients place ahead of the tool catalog so the model reads it before choosing anything.
This server publishes no instructions, or was last inspected before Glama recorded them.
Capabilities
Features and capabilities supported by this server
Protocol revision2025-11-25
| Capability | Details |
|---|---|
| tools | {} |
| resources | {} |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| verilator_compileB | Compile Verilog/SystemVerilog design files to C++ using Verilator |
| verilator_simulateC | Run RTL simulation with automatic testbench generation if needed |
| verilator_testbenchgeneratorA | Generate intelligent testbenches for Verilog/SystemVerilog modules with automatic stimulus generation |
| verilator_naturallanguageC | Process natural language queries about RTL simulation, debugging, and analysis |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |
TDQS
Scored across 4 tools
The tools have distinct primary purposes: compile, simulate, generate testbenches, and handle natural language. However, 'verilator_simulate' can auto-generate testbenches if needed, overlapping with 'verilator_testbenchgenerator', which could be confusing for an agent deciding which tool to use for testbench creation.
All tool names follow the verb_noun pattern (e.g., verilator_compile, verilator_simulate), with 'verilator_' as a consistent prefix. The only deviation is 'verilator_testbenchgenerator' and 'verilator_naturallanguage' which combine two words without a separator, but the pattern is still readable.
With 4 tools, the count is on the low end but appropriate for a focused server covering compilation, simulation, testbench generation, and natural language processing. It feels slightly thin for a full RTL workflow but each tool earns its place.
The server provides essential compile and simulate operations but lacks tools for waveform viewing (e.g., VCD/FSDB dumping), coverage analysis, or linting/static checks. There is a 'natural language' tool for analysis, but concrete operations like setting simulation timeouts, reading simulation results, or writing traces are missing, creating significant gaps for debugging workflows.