A
licenseA
qualityB
maintenanceEnables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.
4
17 npm
Apache 2.0
Verilator MCP Server
by ssql2014
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TDQS
C2.9/5.0
Scored across 4 tools
Disambiguation3/5
The tools have distinct primary purposes: compile, simulate, generate testbenches, and handle natural language. However, 'verilator_simulate' can auto-generate testbenches if needed, overlapping with 'verilator_testbenchgenerator', which could be confusing for an agent deciding which tool to use for testbench creation.
Naming Consistency4/5
All tool names follow the verb_noun pattern (e.g., verilator_compile, verilator_simulate), with 'verilator_' as a consistent prefix. The only deviation is 'verilator_testbenchgenerator' and 'verilator_naturallanguage' which combine two words without a separator, but the pattern is still readable.
Tool Count4/5
With 4 tools, the count is on the low end but appropriate for a focused server covering compilation, simulation, testbench generation, and natural language processing. It feels slightly thin for a full RTL workflow but each tool earns its place.
Completeness2/5
The server provides essential compile and simulate operations but lacks tools for waveform viewing (e.g., VCD/FSDB dumping), coverage analysis, or linting/static checks. There is a 'natural language' tool for analysis, but concrete operations like setting simulation timeouts, reading simulation results, or writing traces are missing, creating significant gaps for debugging workflows.
Maintenance
ActivityInactive
ResponsivenessNo issues