generate_transistor_amplifier
Generate a Micro-Cap .CIR netlist for a common-emitter BJT amplifier with automatic mid-supply biasing, enabling AC, transient, or DC simulation of the gain stage.
Instructions
Draw a .CIR common-emitter BJT gain stage (NPN primitive).
Divider bias, unbypassed emitter degeneration, AC-coupled input. The
midband gain magnitude is Rc/(Re+re') — roughly Rc/Re when Re is
well above the intrinsic re'. By default the R1/R2 divider is
computed to bias the collector at mid-supply, so the stage stays in the
active region for any Rc/Re and the gain is real (a fixed divider
would silently saturate as Rc grows). Rc must exceed Re. Feed
the result to simulate_schematic.
Args:
rc, re: collector and (unbypassed) emitter resistors; their ratio is the
midband gain. Rc must exceed Re.
r1, r2: base bias divider (vcc to base, base to ground); leave unset
to auto-bias for a mid-supply collector, or give both to override.
vcc: supply voltage.
cin: input coupling capacitor.
source: input source VALUE, Micro-Cap syntax ("AC=1" for AC gain).
analysis: AC, Transient, or DC.
output_node: label for the collector output node.
Returns the .CIR text.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| r1 | No | ||
| r2 | No | ||
| rc | No | 4.7K | |
| re | No | 1K | |
| cin | No | 10U | |
| vcc | No | 12 | |
| source | No | AC=1 | |
| analysis | No | AC | |
| output_node | No | OUT |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||