generate_mosfet_amplifier
Create a Micro-Cap .CIR netlist for a common-source MOSFET amplifier with automatic gate biasing. Keeps the transistor in saturation, ensuring accurate gain for simulation.
Instructions
Draw a .CIR common-source MOSFET gain stage (NMOS primitive).
Gate divider bias, source degeneration, AC-coupled input, body tied to
source. Midband gain is -gm*Rd/(1+gm*Rs) — roughly -Rd/Rs when
gm*Rs is large. By default the gate divider is computed from the model's
VTO/KP to bias the drain at mid-supply, so the device stays in
saturation and actually amplifies (a mis-biased MOSFET drops out of
saturation and the gain collapses). Feed the result to simulate_schematic.
Args:
rd, rs: drain and (degeneration) source resistors.
r1, r2: gate bias divider; leave unset to auto-bias for a mid-supply
drain, or give both to override.
vdd: supply voltage.
cin: input coupling capacitor.
source: input source VALUE, Micro-Cap syntax ("AC=1" for AC gain).
analysis: AC, Transient, or DC.
output_node: label for the drain output node.
Returns the .CIR text.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| r1 | No | ||
| r2 | No | ||
| rd | No | 4.7K | |
| rs | No | 1K | |
| cin | No | 10U | |
| vdd | No | 12 | |
| source | No | AC=1 | |
| analysis | No | AC | |
| output_node | No | OUT |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||