Run a SPICE netlist through Micro-Cap and return the waveform data.

The netlist is plain SPICE. Rules that will bite you if ignored:

• Node 0 is ground and must exist. Every node needs a DC path to it, or the run fails to converge.

• A .PRINT line is mandatory — it names the outputs you want. Without it Micro-Cap emits only an operating-point dump and no waveforms.

• Match the analysis to the question: ac for frequency response and gain/phase, transient for time-domain behaviour and start-up, dc for bias points and transfer curves.

• Set the time span from the circuit's own constants. A .TRAN running for 10 s on a circuit with microsecond edges returns a flat line.

• Active parts need their supplies wired; an op-amp without rails does nothing.

Args: netlist: full SPICE deck, first line is the title, ending in .END. analysis: transient | ac | dc | harmonic_distortion | intermodulation_distortion | dynamic_ac | dynamic_dc | stability. defines: values for .DEFINE symbols in the deck, e.g. {"R": "1K"}. max_points: cap on returned samples; the run itself is unaffected.

Returns: Columns, units, sampled data, solver statistics, and any warnings.

Draw a .CIR op-amp amplifier with a near-ideal op-amp.

inverting gives gain -Rf/Rin; non-inverting gives 1 + Rf/Rg. The feedback resistor is sized from gain and rin. Produces a drawn schematic; feed it to simulate_schematic or hand the .CIR to the user.

Args: gain: magnitude of the closed-loop gain (> 0; non-inverting needs >= 1). kind: inverting or non-inverting. rin: input resistor (inverting) or gain resistor to ground (non-inverting); sets the feedback resistor from the gain. source: source VALUE, Micro-Cap syntax ("DC=0 AC=1" for AC). analysis: AC, Transient, or DC. output_node: label for the output node.

Returns the .CIR text.

Draw a .CIR common-emitter BJT gain stage (NPN primitive).

Divider bias, unbypassed emitter degeneration, AC-coupled input. The midband gain magnitude is Rc/(Re+re') — roughly Rc/Re when Re is well above the intrinsic re'. By default the R1/R2 divider is computed to bias the collector at mid-supply, so the stage stays in the active region for any Rc/Re and the gain is real (a fixed divider would silently saturate as Rc grows). Rc must exceed Re. Feed the result to simulate_schematic.

Args: rc, re: collector and (unbypassed) emitter resistors; their ratio is the midband gain. Rc must exceed Re. r1, r2: base bias divider (vcc to base, base to ground); leave unset to auto-bias for a mid-supply collector, or give both to override. vcc: supply voltage. cin: input coupling capacitor. source: input source VALUE, Micro-Cap syntax ("AC=1" for AC gain). analysis: AC, Transient, or DC. output_node: label for the collector output node.

Returns the .CIR text.

Draw a .CIR emitter follower (common-collector BJT buffer).

Collector straight to the supply, output at the emitter. Voltage gain is just under 1 (Re/(Re+re')); the value is current gain and low output impedance — a buffer that drives a heavy load without loading the source. The divider auto-biases the emitter at mid-supply so it can swing both ways. Feed the result to simulate_schematic.

Args: re: emitter resistor (sets the bias current Vcc/2 / Re). r1, r2: base bias divider; leave unset to auto-bias, or give both. vcc: supply voltage. cin: input coupling capacitor. source: input source VALUE, Micro-Cap syntax. analysis: AC, Transient, or DC. output_node: label for the emitter output node.

Returns the .CIR text.

Draw a .CIR common-source MOSFET gain stage (NMOS primitive).

Gate divider bias, source degeneration, AC-coupled input, body tied to source. Midband gain is -gm*Rd/(1+gm*Rs) — roughly -Rd/Rs when gm*Rs is large. By default the gate divider is computed from the model's VTO/KP to bias the drain at mid-supply, so the device stays in saturation and actually amplifies (a mis-biased MOSFET drops out of saturation and the gain collapses). Feed the result to simulate_schematic.

Args: rd, rs: drain and (degeneration) source resistors. r1, r2: gate bias divider; leave unset to auto-bias for a mid-supply drain, or give both to override. vdd: supply voltage. cin: input coupling capacitor. source: input source VALUE, Micro-Cap syntax ("AC=1" for AC gain). analysis: AC, Transient, or DC. output_node: label for the drain output node.

Returns the .CIR text.

Draw a .CIR BJT long-tailed (differential) pair.

Two matched NPN sharing an emitter tail resistor to ground, each collector loaded by Rc. Single-ended drive on one base; the collectors OUTP and OUTN swing in antiphase, each with magnitude Rc/(2*re'). The common-mode base voltage and tail resistor are auto-sized to bias both collectors near mid-supply, so the pair is balanced and in the active region — the differential gain then works out near Vcc/(4*Vt), set by the supply rather than by Rc. Both collectors are labelled; the default trace plots OUTP (edit it to plot OUTN).

Args: rc: collector load on each side. rt: emitter tail resistor; leave unset to auto-size for mid-supply. vcc: supply voltage. vb: common-mode base voltage; leave unset for vcc/2. source: AC drive VALUE for the input base ("AC=1"). analysis: AC, Transient, or DC. output_node: which collector the default trace plots (OUTP/OUTN).

Returns the .CIR text.

Draw a .CIR BJT current mirror.

A diode-connected NPN sets a reference current Iref = (Vcc - Vbe)/Rref; a matched NPN copies it into Rload. The mirrored current is Iout ≈ Iref (a few % high from the Early effect). It is a DC bias block, so run a transient/DC and read V(OUTC): the mirrored current is (Vcc - V(OUTC)) / Rload.

Args: rref: reference-leg resistor; sets Iref. rload: load on the output transistor's collector. vcc: supply voltage. analysis: transient or dc (it is a bias block, not an AC stage). output_node: label for the output collector node.

Returns the .CIR text.

Draw a .CIR cascode amplifier (common-emitter under common-base).

A common-emitter transistor stacked under a common-base transistor. The midband gain is the common-emitter's, -Rc/(Re+re'), but the upper transistor shields the lower one's collector from the output swing, so the Miller capacitance nearly vanishes and both output impedance and bandwidth rise — the reason to use a cascode over a plain common-emitter. All bias points are computed for a mid-supply output with active-region headroom, and both bases are driven by sources carrying their DC bias directly (no coupling caps or dividers). Rc must exceed Re.

Args: rc, re: collector load and emitter degeneration; their ratio is the gain. vcc: supply voltage. source: AC drive VALUE added to the lower base's bias ("AC=1"). analysis: AC, Transient, or DC. output_node: label for the output node (the upper collector).

Returns the .CIR text.

Draw a .CIR schematic: a voltage source driving parts in series to ground, optionally with parallel branches from the output node to ground.

Unlike a netlist, this produces a drawn schematic you can open in Micro-Cap. Feed the result to simulate_schematic to run it, or hand the .CIR text to the user.

Bounded on purpose — a source, a series chain of two-terminal passives (R, C, L), and optional parallel shunt branches. That covers RC/RL/RLC, dividers, and resonant tanks. Every pin position is taken from Micro-Cap's own component library, so the drawn circuit is electrically what you asked for. For an op-amp gain stage use generate_amplifier; for a common-emitter BJT stage use generate_transistor_amplifier.

Args: parts: ordered "KIND=VALUE" strings in series, KIND in R/C/L, e.g. ["R=1K", "C=159.155N"] for an RC low-pass. With shunt, the whole chain feeds the output node. source: the source's VALUE in Micro-Cap syntax — "DC=0 AC=1" for an AC probe, or a PULSE ... line for transient. analysis: AC, Transient, or DC. output_node: label for the output node. shunt: extra "KIND=VALUE" strings hung in parallel from the output node to ground, e.g. ["L=1M", "C=1U"] on a series R for a tank.

Returns the .CIR text and the ordered part references.

Run a Micro-Cap .CIR schematic and return its data.

Use this to adapt a reference: fetch one with get_example (its format will be microcap_schematic), change a component value or two in the text, and run the modified schematic here. simulate is for plain SPICE netlists; this is for the coordinate-carrying .CIR format.

Numeric export is switched on automatically, NPts is overridden to points (the shipped setting is often 0, which exports one row), and the symbolic transient bound TMIN is repaired for batch mode — all the things that make a stock schematic yield no data otherwise.

Args: schematic: full .CIR text. analysis: which of the circuit's analyses to run. defines: values for any .DEFINE symbols the schematic uses. points: resolution to compute at; see simulate_example. max_points: cap on returned samples.

Run one netlist repeatedly, varying a .DEFINE parameter.

The deck must declare the symbol, e.g. .DEFINE RLOAD 1K, and use it in a component value. Each value is a separate Micro-Cap run.

Args: netlist: SPICE deck containing a .DEFINE for parameter. parameter: the symbol to vary. values: values to substitute, e.g. ["1K", "10K", "100K"]. analysis: analysis to run for every value. max_points: cap on returned samples per run.

Run a netlist and return Micro-Cap's own rendered plot as a JPEG image.

Use this to look at a waveform. For numbers to reason about, use simulate — reading values off a picture is guesswork.

Render a .CIR schematic as an SVG picture — the drawing, not a plot.

Micro-Cap's own schematic-image command does not work in batch, so this draws the circuit directly from the .CIR (the same placements, wires and node labels), giving recognisable symbols for R/C/L, sources, ground, BJT/MOSFET and op-amp. Use it to see a circuit — a reference you fetched or one drawn by the generators — without opening Micro-Cap. No simulation runs.

Returns SVG (vector, self-contained); save it as .svg or embed it.

Render the schematic as SVG with each labelled node's DC operating-point voltage written beside it — a marked-up drawing you can read the bias off.

Runs the DC operating point (a short transient at t=0), reads the voltage at every [Grid Text] node the schematic labels (IN, OUT, OUTP…), and overlays them on the drawing. Best on the generated stages and other circuits that hold a stable operating point.

Run a .CIR schematic and return Micro-Cap's rendered plot as a JPEG.

The picture companion to simulate_schematic: use it to look at the response of a schematic — a reference circuit you edited, or one drawn by generate_transistor_amplifier / generate_differential_pair / the other generators. For numbers to reason about, use simulate_schematic.

Run one of Micro-Cap's own reference circuits and return its data.

These are worked designs by the tool's authors, so this is the cheapest way to get a trustworthy baseline before modifying anything. Use describe_example first to see which analyses a circuit supports and what it plots — asking for an analysis it was not built for returns nothing useful.

Numeric export is enabled automatically; the shipped circuits have it off.

Args: name: reference circuit name. analysis: which analysis to run. max_points: cap on returned samples. points: resolution to compute at. The reference circuits carry their own display setting, often tiny or 0 — which exports a single useless row and makes an oscillator look dead. Overriding it is what makes the library usable as data; only lower it if you specifically want the circuit's own resolution.

Report what a reference circuit is set up to do, without running it.

Returns the analyses it defines and the expressions it plots. Read this before simulate_example so you ask for an analysis that exists.

List the circuit-design domains Micro-Cap ships reference circuits for.

Returns domain name -> circuit count. Start here before designing from scratch: a working reference beats an invented topology.

Search the ~470 reference circuits by name or domain.

Fetch one reference circuit's source text.

.CKT files are plain SPICE and can be fed straight to simulate. .CIR files are Micro-Cap schematics: text, but carrying component coordinates and analysis settings as well as the netlist.