simulate_verilog
Execute Verilog code simulations with Icarus Verilog to test hardware designs by providing both design and testbench code for functional verification.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| verilog_code | Yes | The Verilog design code | |
| testbench_code | Yes | The testbench code |