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EDA Tools MCP Server

by kfy123bot

run_openlane

Execute the complete ASIC design flow from RTL to GDSII using OpenLane for chip implementation.

Instructions

Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes.

Input Schema

TableJSON Schema
NameRequiredDescriptionDefault
verilog_codeYesThe Verilog RTL code for ASIC implementation
design_nameYesName of the design (will be used for module and files)
clock_portNoName of the clock portclk
clock_periodNoClock period in nanoseconds
open_in_klayoutNoAutomatically open result in KLayout
Behavior3/5

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations provided, the description carries full burden. It discloses the time-consuming nature ('up to 10 minutes'), which is valuable behavioral context. However, it doesn't mention other important traits like whether it creates files/directories, requires specific permissions, handles errors, or provides progress feedback. The description adds some context but leaves significant gaps.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Conciseness5/5

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is perfectly concise with two sentences that each earn their place: the first states the core purpose, the second provides critical behavioral context (time estimate). No wasted words, well-structured and front-loaded.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Completeness3/5

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

Given this is a complex ASIC design tool with 5 parameters, no annotations, and no output schema, the description is incomplete. While it covers purpose and time estimate, it doesn't address what the tool returns (GDSII file? success status?), error handling, or prerequisites. For a tool of this complexity with no structured support, more context would be helpful.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Parameters3/5

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 100%, so the schema already documents all 5 parameters thoroughly. The description doesn't add any parameter-specific information beyond what's in the schema. According to scoring rules, when schema_description_coverage is high (>80%), the baseline is 3 even with no param info in description.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Purpose5/5

Does the description clearly state what the tool does and how it differs from similar tools?

The description clearly states the tool's purpose with specific verb ('Run') and resource ('complete ASIC design flow using OpenLane'), and distinguishes it from siblings by specifying the full RTL to GDSII process. This differentiates it from tools like synthesize_verilog (partial flow) or view_gds (viewing only).

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Usage Guidelines3/5

Does the description explain when to use this tool, when not to, or what alternatives exist?

The description implies usage context through the time estimate ('up to 10 minutes'), suggesting this is for full ASIC implementation rather than partial steps. However, it doesn't explicitly state when to use this vs. alternatives like synthesize_verilog or when not to use it (e.g., for quick simulations). The context is implied but not explicit.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.

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