run_openlane
Execute the complete ASIC design flow from RTL to GDSII using OpenLane for chip implementation.
Instructions
Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| verilog_code | Yes | The Verilog RTL code for ASIC implementation | |
| design_name | Yes | Name of the design (will be used for module and files) | |
| clock_port | No | Name of the clock port | clk |
| clock_period | No | Clock period in nanoseconds | |
| open_in_klayout | No | Automatically open result in KLayout |