EDA Tools MCP Server
Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
| HOME | No | Home directory path (e.g., /your/home/directory) | |
| PATH | No | System PATH environment variable to locate EDA tools (e.g., /usr/local/bin:/opt/homebrew/bin:/usr/bin:/bin) |
Instructions
Guidance the server publishes about itself, which clients place ahead of the tool catalog so the model reads it before choosing anything.
This server publishes no instructions, or was last inspected before Glama recorded them.
Capabilities
Features and capabilities supported by this server
Protocol revision2025-11-25
| Capability | Details |
|---|---|
| tools | {} |
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| synthesize_verilogC | Synthesize Verilog code using Yosys for various FPGA targets |
| simulate_verilogC | Simulate Verilog code using Icarus Verilog |
| view_waveformB | Open VCD waveform file in GTKWave viewer |
| run_openlaneA | Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes. |
| view_gdsC | Open GDSII file in KLayout viewer |
| read_openlane_reportsB | Read OpenLane report files for LLM analysis. Returns all reports or specific category for detailed analysis of PPA metrics, timing, routing quality, and other design results. |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |
TDQS
Scored across 6 tools
Each tool has a clearly distinct purpose with no overlap: reading reports, running a full design flow, simulating, synthesizing, viewing GDSII files, and viewing waveforms. The descriptions specify unique actions and tools (OpenLane, Icarus Verilog, Yosys, KLayout, GTKWave), making misselection unlikely.
All tools follow a consistent verb_noun pattern (e.g., read_openlane_reports, run_openlane, simulate_verilog) with no deviations. The naming is uniform and predictable across the set, using snake_case throughout.
With 6 tools, the count is well-scoped for an EDA server, covering key stages like simulation, synthesis, viewing, and analysis. Each tool earns its place by addressing a specific need in the ASIC/FPGA design workflow without being excessive or sparse.
The tool set covers major EDA operations: simulation, synthesis, viewing, and report analysis, with no dead ends. A minor gap exists in lacking explicit CRUD operations for design files (e.g., create/edit Verilog), but agents can work around this using the provided tools for core workflows.