Get a2n.EasyEDA MCP connection status, the active mode (online/offline/hybrid), and current project info.

Set the component sourcing mode. "offline" = local/system libraries only. "online" = EasyEDA backend search. "hybrid" = local first then online.

Read the current EasyEDA project tree (boards, schematics, pages with UUIDs) and metadata.

Open a document (schematic, schematic page, PCB) by its UUID from the project tree.

Advanced: call any low-level EasyEDA handler method directly by name with a params object. Use when no dedicated tool exists. Method names follow the "domain.action.target" convention (e.g. "pcb.create.via", "sch.wire.create", "lib.device.search").

Dev/advanced: invoke ANY eda.* API by dotted path without changing the extension. e.g. path="sch_ManufactureData.getExportDocumentFile", args=["sch","PNG",{},"Current Schematic Page"]. New capabilities can be prototyped Node-side only (no extension reinstall). File results return as base64; image files are shown directly.

Read this FIRST. Conventions and recommended workflow for driving EasyEDA via this MCP: coordinate system, net-by-name wiring, schematic vs PCB context, and the place -> wire -> verify loop.

Get all schematic components (parts, net flags, net ports, etc.) with positions, rotation, designators.

Get all pins of a schematic component by its primitive ID.

Get all wires in the schematic, optionally filtered by net name(s).

Get the schematic netlist in the specified format.

Read the current schematic as a structured circuit (components + pins + resolved net per pin). Best high-level read.

Validate schematic connectivity from the resolved circuit: reports floating (unconnected) pins, single-pin nets (likely dangling), and a per-net summary. Read-only diagnostic that complements the place -> wire -> verify loop. No EasyEDA write is performed.

Get all currently selected primitives in the schematic editor.

Run Design Rule Check (DRC) on the schematic.

Export the FULL schematic sheet as a PNG (whole A4 page: border, title block, and every component) — reproducing EasyEDA's "Export -> PNG" with true colors, via Chrome DevTools Protocol. Not a viewport screenshot: it reads the schematic SVG, reframes to the full content, and rasterizes. Requires EasyEDA Pro launched with remote debugging (run-easyeda-debug.bat / README) and an open schematic page. The image is returned inline; pass "fileName" to ALSO save it to disk.

Search for a component using EasyEDA libraries. In offline mode searches local/system libraries; in online/hybrid mode also queries the EasyEDA backend. Returns device uuid + libraryUuid for placement.

Place a schematic component from a library at a position. Provide device uuid + libraryUuid (from sch_search_component). Use libraryUuid "lcsc" with a device uuid for online placement.

Create a wire on the schematic. "line" is a flat coordinate array [x1,y1,x2,y2,...].

Create a net flag (e.g. VCC/GND short symbol) attached to a net at a position.

Delete one or more schematic components by primitive ID(s).

High-level: place a list of components and auto-wire them locally by net name. No external server, no AI. Components are placed at free positions; pins sharing a net are wired, and VCC/GND/net-port symbols are auto-inserted. Ideal for generating a schematic from a parts+nets list.

Create a new schematic in the current project. Returns the first page uuid.

Create a new page under an existing schematic.

Save the current schematic document.

Save a checkpoint of the current document for later restore.

List saved checkpoints.

Restore a checkpoint by id (or the latest if omitted).

Get all PCB components, optionally filtered by layer.

Get all pads/pins of a PCB component by primitive ID.

Get all net names on the PCB.

Get total routed length of a net.

Get all PCB layers and their properties.

Get all currently selected PCB primitives.

Create a single track segment between two points on a layer/net.

Create a via at a position.

Create a copper pour region on a layer/net.

Move/rotate a PCB component, optionally flip layer, set lock or designator.

Delete one or more PCB primitives by type and IDs.

Run Design Rule Check on the PCB.

Set the number of copper layers (e.g. 2, 4, 6).

Highlight a net on the PCB.

Export Gerber files (returned as base64).

Export BOM file (returned as base64).

Export pick-and-place (centroid) file for assembly (returned as base64). Requires a PCB document active.

Export the PCB layout to PDF (returned as base64). Requires a PCB document active.

Export a 3D model file of the PCB (e.g. STEP). Returned as base64. Requires a PCB document active.

Get the PCB board outline / dimensions (shape, width, height). Requires a PCB document to be active.

Save the current PCB document.