Enables automation of Intel/Altera Quartus FPGA design flow including project management, compilation, simulation, timing analysis, and programming via Claude Code.
A lean MCP server that lets AI agents drive Xilinx Vivado for synthesis, implementation, simulation, and diagnostics through 30 curated tools and raw Tcl execution.
Enables AI assistants to drive Xilinx Vivado, Intel Quartus, and Anlogic TangDynasty for FPGA development, including project creation, synthesis, implementation, timing closure, and hardware programming through natural language.
Provides LLM clients a safe, structured interface to Intel Quartus Prime 25.1 FPGA flows, enabling linting, simulation, and asynchronous compilation with results returned as concise JSON.
MCP server for AMD Xilinx Vivado 2023.1 that enables Claude Code to act as an AI FPGA engineer, providing 27 tools for querying, building, simulating, and programming FPGA designs.