stm32_build_and_flash

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations, the description must carry the full behavioral burden. It does well on what the operation does (compile, then flash over ST-Link, optional clean/reset/verify), but omits key traits: that it overwrites the board's existing flash (destructive), whether flashing is skipped when compilation fails, and the need for a connected probe.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is front-loaded with the one-line purpose, followed by a short explanation and a compact Args block for the six fields, plus a returns line. Nothing is padded, and the primary guidance appears before the supporting detail.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

An output schema exists, so return-value detail is not required, and the parameters are well covered. What is missing is the failure and prerequisite behavior that an agent needs before invoking a hardware-mutating tool with no annotations: probe connection requirements and what happens on a failed build.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

Schema description coverage is 0%, so the description must compensate, and the Args block documents all six parameters: the absolute CubeIDE project root path, the "Debug"/"Release" configuration values that the plain string schema does not constrain, and the probe identifier formats (board nickname, probe nickname, or ST-Link serial number). Remaining flags are described only by restating their titles.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Does the description clearly state what the tool does and how it differs from similar tools?

States specific verbs and resources: it compiles the project and flashes the resulting .elf to a connected STM32 via ST-Link, in one step. It further distinguishes itself from the sibling stm32_build and stm32_flash tools by declaring it is the preferred combined workflow.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Does the description explain when to use this tool, when not to, or what alternatives exist?

Explicitly says this is the most common workflow and should be used instead of calling stm32_build and stm32_flash separately, naming the alternatives directly. It doesn't say when to prefer the split calls (for example, build-only for compile checks), leaving that to inference.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.