Generate standard SPICE netlist
easyeda_generate_spice_netlistGenerates a SPICE netlist (.cir/.sp) from an EasyEDA Pro schematic with ground-to-0 mapping, RLC and semiconductor models, and .op, .tran, .ac, or .dc directives for ngspice, LTspice, or Xyce.
Instructions
Generates a syntactically valid SPICE circuit netlist (.cir / .sp) with ground-to-0 normalization, primitive RLC elements, semiconductor models, and configurable analysis directives (.op, .tran, .ac, .dc) for simulation in ngspice, LTspice, or Xyce.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| target | No | ||
| fileName | No | Optional output file name without extension. | |
| groundNet | No | Net name to map to SPICE datum node 0. | GND |
| timeoutMs | No | ||
| analysisType | No | Simulation analysis type (.op, .tran, .ac, .dc). | op |
| analysisParams | No | Custom analysis directive arguments (e.g. '1u 10m' for .tran, or '10 1 1Meg' for .ac). | |
| destinationPath | No | Optional destination directory / target path. | |
| includeSubcircuits | No | Whether to include X subcircuit cards for ICs. | |
| includeDefaultModels | No | Include built-in generic diode and BJT .model cards. |