Checks whether the EasyEDA Pro extension is connected and reports active document/capability information.

Returns a structured diagnosis of the local MCP bridge, EasyEDA Pro extension connection state, protocol compatibility, active document context, and suggested next steps.

Summarizes active project, active document, selection, and editor context from the open EasyEDA Pro instance.

Returns components, pins, or primitives currently selected by the user on the active schematic or PCB canvas.

Finds a component by designator, name, value, footprint, or property in the active EasyEDA Pro project.

Finds a net by name and returns available connections or metadata from the active project.

Returns components, pins, nets, wires, labels and provenance. Single-page reads attempt native Protel2 netlist membership and explicitly report geometric fallback.

Queries native schematic nets from EasyEDA Pro per-sheet or project-wide. Distinguishes native net connectivity from geometric inferences.

Lists normalized schematic components with designator, value/name, footprint, position, and key properties.

Returns all known pins for a schematic component, including pin number, pin name, position, and net when available.

Traces net topology, connected pins, wire primitive counts, and connectivity evidence across schematic sheets.

Traces component pins, connected nets, adjacent components, and confidence ratings for schematic debugging.

Scans active schematic sheets for unconnected component pins, reporting potential schematic omissions or dangling inputs.

Executes native EasyEDA Pro schematic Electrical Rules Check (ERC) on the active document, reporting rule violations, unconnected pins, and design errors.

Evaluates essential circuit patterns around a focus component or region, including power, ground, decoupling, pull-ups, and floating pin rules.

Runs generic read-only connection assertions against the active schematic, including pin/net checks and passive paths through resistors, capacitors, inductors, diodes, or LEDs.

Inspects net ports (hierarchical/global sheet connectors), multi-bit buses, and bus entry taps in the active schematic with connection validation and signal range diagnostics.

Performs cross-domain discrepancy analysis between Schematic and PCB in EasyEDA Pro. Detects unplaced components, untracked PCB parts, footprint mismatches, pin/pad count discrepancies, unrouted nets, and overall synchronicity score.

Executes the native EasyEDA Pro PCB Design Rule Check (DRC) on the active board and reports detailed violations, categorized counts, evidence, document target, and execution comparison.

Returns the layer stackup and configuration of the active EasyEDA Pro PCB, including signal/copper layers, mechanical layers, colors, and visibility.

Analyzes the PCB routing status, total nets, completion percentage, unrouted net connections (ratsnest), and optional net lengths.

Lists normalized PCB components with designator, footprint, placement layer, coordinates, and rotation angle.

Inspects PCB pads (both component footprint pins and free pads) with net connections, layers, drill sizes, shapes, and coordinates.

Prepares a component transformation on the PCB (move, rotate, flip, or delete) with preview, scope, expected coordinates, and exact confirmation phrase. Does not modify the PCB until confirmed.

Inspects the board outline boundary, bounding box (minX, minY, maxX, maxY, width, height), perimeter, estimated area, loop closure status, and segments on the active PCB.

Prepares creation, rectangular/polygonal sizing, clearing, or segment modification of the board outline on the active PCB. Returns a mutationId and exact confirmation phrase required for execution via easyeda_confirmed_action.

Prepares native auto-routing or destructive unrouting of tracks/vias on the active PCB canvas with explicit nets scope, safety preview, and exact confirmation phrase. Does not modify the PCB until confirmed.

Prepares native component auto-placement/auto-layout on the active PCB canvas within the board outline with safety preview and exact confirmation phrase. Does not modify the PCB until confirmed.

Lists and inspects copper tracks and traces on the active PCB layout with net, layer, geometry coordinates, width, and calculated length.

Lists and inspects vias on the active PCB layout with net, center coordinates (x, y in mm), outer diameter, hole/drill diameter, and layers.

Prepares creating, modifying, or destructively deleting copper tracks and vias on the active PCB canvas with safety preview and exact confirmation phrase. Does not modify the PCB until confirmed.

Visually highlights a specified net on the EasyEDA Pro PCB canvas, or clears all highlighted nets.

Lists and inspects copper zones (copper pours/areas) on the active PCB layout with net, layer, clearance, fillType, vertices, and bounding box.

Lists and inspects keepout areas on the active PCB layout with layer, keepoutType, vertices, and bounding box.

Prepares creating, modifying, deleting, or recalculating/rebuilding copper zones and keepouts on the active PCB canvas with safety preview and exact confirmation phrase. Does not modify the PCB until confirmed.

Inspects unrouted ratsnest airwire lines on the active PCB layout with endpoints, coordinates, lengths, and inference method/tolerances.

Generates a comprehensive component placement report including density, bounding boxes, layer distribution, and collision/clearance warnings.

Generates detailed physical metrics for nets on the active PCB (pad counts, track length, via count, copper zone coverage, and completion percentage).

Lists net classes and their member net assignments, routing rules (trace width, clearance, via size) on the active PCB.

Lists differential pairs with positive and negative net assignments, target impedance, trace width, gap, actual routed track lengths, and skew tolerance compliance.

Lists equal length matching groups with member net lengths, reference length, max skew, and tolerance compliance.

Prepares creating, modifying, or deleting net classes, differential pairs, or equal length groups with safety preview, API capability check, and exact confirmation phrase. Does not modify the PCB until confirmed.

Inspects 3D models, vertical board envelope (substrate thickness, top/bottom max heights, total enclosure clearance), missing STEP/OBJ models ranked by criticality, and 3D spatial interference collisions between components on the active PCB.

Retrieves 3D camera angles, rendering layer visibility, STEP/OBJ 3D export support, and shortcuts to open the native 3D WebGL viewport.

Validates and stages external layout or routing files (Specctra SES, EasyEDA router JSON, EasyEDA layout JSON, DXF) with geometry validation, safety preview, and exact confirmation phrase. Does not modify the PCB until confirmed.

Read native EasyEDA Pro PCB design rules for current or configured scopes. Does not mutate the board.

Prepare an explicit, reviewable edit for native EasyEDA Pro PCB design rules. Returns target identity, baseline snapshot, editId and the exact required confirmation string.

Query a retained DRC edit after execution or timeout. Never reapply an uncertain edit. Results live only in this extension instance.

Navigates/highlights a component in the EasyEDA Pro editor when the extension can locate it.

Navigates to coordinates or a rectangular region in the active EasyEDA Pro PCB/document.

Zooms the active PCB editor to the board outline.

Exports a BOM from the active EasyEDA Pro project through the extension.

Exports a netlist from the active EasyEDA Pro schematic or PCB through the extension.

Exports Gerber fabrication files from the active EasyEDA Pro PCB through the extension.

Exports a PDF from the active EasyEDA Pro document through the extension.

Exports the Pick and Place / Centroid (CPL) file from the active EasyEDA Pro PCB for SMT assembly (e.g. JLCPCB).

Exports a high-resolution visual rendering or vector graphic (PNG, SVG, JPG) of the active schematic sheet or PCB layer stack with transparent background, resolution scaling, and layer visibility options.

Exports 3D mechanical CAD geometry (STEP, OBJ, STL, WRL) of the board and mounted component bodies for MCAD integration, 3D printing, and thermal/clearance analysis.

Exports the entire EasyEDA Pro project archive (epro, zip, json) containing all schematic sheets, PCB layout, layer configurations, netlists, and project metadata with integrity validation.

Exports 2D CAD DXF drawings of PCB outlines, copper traces, drilling holes, or schematic drawings for mechanical enclosures, CNC routing, laser cutting, and AutoCAD integration.

Searches the EasyEDA / LCSC component catalog by keyword, LCSC part number (e.g. C1523), or manufacturer part number.

Fetches complete device definition, schematic symbol pinout, PCB footprint pad geometry, and pin-to-pad correspondence mapping by device UUID, LCSC part code (e.g. C1523), or placed component designator (e.g. U1).

Compares two component devices (by UUID, LCSC code, or designator) evaluating pinout matching, footprint geometry, JLCPCB stock availability, and drop-in replacement feasibility.

Validates 1-to-1 correspondence between schematic symbol pins and PCB footprint pads across all components on active canvas or for a specific component. Identifies unmapped pins, unmapped pads, and potential netlist connectivity breaks.

Lists all documents belonging to the current EasyEDA Pro project and open editor tabs, detailing document identity, type, open/active status, and tab layout.

Opens a document or activates an open tab in EasyEDA Pro, shifting input focus and canvas viewport. Provides readback confirmation and reports focus transition.

Captures the visible canvas rendering viewport image in EasyEDA Pro (via DMT_EditorControl). Explicitly documents viewport limits and asserts target match.

Prepares a create, move, update, or delete operation on a schematic component with full preview, ID/designator resolution, and exact confirmation phrase. Does not modify the schematic until confirmed via easyeda_confirmed_action.

Prepares a wire creation, modification, deletion, or net label placement operation in EasyEDA Pro with preview, coordinate validation, affected connections check, and exact confirmation phrase. Does not write until confirmed.

Prepares a create, modify, or delete operation on a schematic net port (hierarchical/sheet connector) with preview, validation, and exact confirmation phrase. Does not write until confirmed via easyeda_confirmed_action.

Prepares a create, modify, or delete operation on schematic multi-bit buses or diagonal bus entries with syntax parsing, coordinate validation, preview, and exact confirmation phrase. Does not write until confirmed via easyeda_confirmed_action.

Prepares a synchronization or board creation mutation between Schematic and PCB in EasyEDA Pro ('syncToPcb', 'syncToSchematic', 'createPcbFromSchematic') with cross-domain discrepancy preview and exact confirmation phrase. Does not write until confirmed via easyeda_confirmed_action.

Queries the status, readback evidence, and verification of any prepared or applied mutation by mutationId. Safe and read-only; never automatically replays a mutation.

Runs a mutating EasyEDA Pro action after human approval. For editDrcRules pass params:{editId} and the exact prepared confirmation. Saving the PCB remains separate.

Performs feasibility evaluation of analog SPICE simulation on the active schematic: audits component SPICE model availability, verifies Node 0 / GND reference, checks stimulus sources, and documents engine limits and platform boundaries.

Generates a syntactically valid SPICE circuit netlist (.cir / .sp) with ground-to-0 normalization, primitive RLC elements, semiconductor models, and configurable analysis directives (.op, .tran, .ac, .dc) for simulation in ngspice, LTspice, or Xyce.