generate_project_pdw
Compile ladder-logic IR into FBs-20MC/32MC/40MC/60MC PDW project layouts from a local template, replacing programs and annotations while preserving opaque settings and writing new files only.
Instructions
Compile Ladder IR to sampled FBs-20MC/32MC/40MC/60MC PDW layouts.
Module records come from local templates.
Match ladder.profile to the template CPU. Template must be inside workspace. Program and
annotations are replaced by the explicit request; opaque project settings are retained.
Network.comment supports CR/LF. Section indexes refer to zero-based source networks.
Optional embedded SECT text uses only the sampled even-byte encoding. FUNC199 and
control flow are not generated. New files only, no PLC connection or GUI guarantee.
module_order=null preserves all modules; [] removes them explicitly. Names copy exact
records from the template and optional workspace-scoped module_template_paths. Order and
duplicates are retained. Missing or conflicting records are rejected. No automatic I/O
allocation, module parameter editing, slot-capacity or hardware compatibility validation.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"output_name": "<output_name>",
"template_path": "<template_path>",
"ladder": "<ladder>",
"io_contract": "<io_contract>"
},
"name": "generate_project_pdw"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ladder | Yes | ||
| comments | No | ||
| sections | No | ||
| acceptance | No | ||
| io_contract | Yes | ||
| output_name | Yes | ||
| module_order | No | ||
| template_path | Yes | ||
| require_acceptance | No | ||
| module_template_paths | No |