Includes build/version, generation and simulation scope, architecture policy, workspace,
    output directory and artifact delivery. detail=true expands instruction-specific limits.
    This never reads or modifies program content; use modify_network to edit one network.
    PLC access and artifact rename/delete are intentionally outside this offline server.
    

    Omit family to discover valid identifiers; provide one returned identifier for its operand,
    encoding and runtime-model boundaries. Use this for implemented MCP coverage, not general
    PLC legality: get_manual_reference provides manual maxima and edition differences, while
    get_capabilities provides server-wide support. Unknown family identifiers return an error.
    

    Use this to decide documented PLC legality, manual-edition differences or RTC register and
    control procedures. Use get_instruction_capabilities instead for implemented encoder and
    simulation coverage, or get_design_guide for generation workflow. This reads no project or
    PLC state and returns static reference data only.
    

    Use this after obtaining R4128..R4134 externally; optionally include packed R4135 to check
    hour/minute consistency. It checks field ranges and month/day, then returns decoded fields,
    expected_R4135 and consistency when supplied. Invalid or unknown fields return an error and
    nothing is written. This server has no PLC-access tool; use get_manual_reference for RTC
    register meanings and setting procedure.
    

    Use this before generation to choose a control, sequence, system or custom-Ladder tool and
    to obtain acceptance-test patterns. With detail=false it returns compact control recipes,
    architecture policy and workflow; detail=true adds instruction notes, complete examples
    and the Ladder IR schema. This is not runtime capability metadata (get_capabilities),
    instruction operand evidence (get_instruction_capabilities), or manual/RTC reference data
    (get_manual_reference), and it does not validate IR or create a file.
    

    Never use this for one recipe, dependent ordered steps or caller-authored IR: use
    generate_control_ldr, generate_sequence_ldr or generate_ldr respectively. This tool
    allocates internal M/T/C, permits shared inputs, rejects explicit overlaps, checks
    acceptance and writes only a new artifact. Validation failure writes nothing. It does not
    execute existing IR or return a trace; use simulate_ladder for that.
    

    Never use this for multiple independent controls, ordered steps or caller-authored IR: use
    generate_system_ldr, generate_sequence_ldr or generate_ldr respectively. Supports latch,
    toggle, edges, delays, pulse, counter, direction interlock and star/delta. Physical I/O must
    be explicit; validation failure writes nothing. generate_component_comments creates only a
    separate comment-import .txt.
    

    Never use this for one control, independent controls or caller-authored IR: use
    generate_control_ldr, generate_system_ldr or generate_ldr respectively. validate_ladder
    checks existing IR and cannot derive steps. Uses native T timers or FUN87 register state for
    pause/resume, never adds X/Y, and requires an explicit clock for pulse counting. Validation
    failure writes nothing; no GUI or PLC verification is implied.
    

    Never translate a ControlSpec, SequenceSpec or SystemSpec to call this tool; use
    generate_control_ldr, generate_sequence_ldr or generate_system_ldr. It does not design
    recipes, resolve defaults or allocate recipe resources. generate_component_comments creates
    only a separate comment .txt. Returns SHA-256, a resource link and warnings; validation
    failure writes nothing and existing files are never overwritten.
    

    Use this for CPU/profile data, modules, sections, Chinese comments, network offsets and
    known checksums. It does not return the downloadable binary; use get_pdw_artifact for exact
    generated bytes. FUNC199 and unsupported layouts remain opaque, invalid files return an
    error, and nothing is written or sent to a PLC.
    

    Supply an existing local PDW as template_path and a different output_name; opaque project
    settings are retained while requested program and annotations are replaced. This writes a
    variable-length PDW binary with optional embedded sections and comments;
    generate_component_comments writes only a separate comment-import .txt and cannot create a
    PDW project. Sampled FBs-20MC/32MC/40MC/60MC layouts are supported.

    Module records come from local templates.

    Match ladder.profile to the template CPU. Template must be inside workspace.
    Network.comment supports CR/LF. Section indexes refer to zero-based source networks.
    Optional embedded SECT text uses only the sampled even-byte encoding. FUNC199 and
    control flow are not generated. New files only, no PLC connection or GUI guarantee.
    module_order=null preserves all modules; [] removes them explicitly. Names copy exact
    records from the template and optional workspace-scoped module_template_paths. Order and
    duplicates are retained. Missing or conflicting records are rejected. No automatic I/O
    allocation, module parameter editing, slot-capacity or hardware compatibility validation.
    

    Same rung count required. Only X0/X1, Y0/Y1/Y2 and NO/NC contacts supported.
    No branches, functions, comments or PLC operations. Templates are workspace-scoped.
    This generates a PDW binary; generate_component_comments produces only a separate .txt.
    Keep private templates outside Git; configure --root to their private directory.
    Return the actual binary artifact and warnings. Never overwrite.
    

    Use this after PDW generation when the client needs an embedded binary resource; use
    inspect_pdw to interpret project structure, or get_ldr_artifact for an .ldr. output_name
    must be the exact plain .pdw filename in the artifact directory. Missing, oversized or
    wrong-extension files return an error. This reads only and returns URI, size and SHA-256.
    

    Call this only when the user explicitly requests 新增元件註解 or component comments. It
    does not inspect, analyze, generate or modify ladder logic or PDW projects; use analyze_ldr
    to explain the logic and device references in an existing .ldr.
    Rows use REF/COMMENT/DESCRIPTION, tabs, CRLF and CP950/Big5; COMMENT is at most 16
    encoded bytes. Never overwrites a file.
    

    Use the original output_name, including .ldr. Returns exact file bytes as base64
    with SHA-256; only reads the configured output directory. Useful when the client
    cannot access local server paths or cannot invoke resources/read directly.
    

    Use this for framing, record offsets, raw payload bytes and stored/calculated CRC evidence.
    It reads one workspace-scoped file and returns metadata only; it never writes or connects to
    a PLC. Use read_ldr for decoded networks or analyze_ldr for device reads, writes and
    meaning.
    Invalid framing or file constraints return an error rather than partial interpretation.
    

    Use this for decoded logic and raw payloads; use inspect_ldr for container offsets or
    bad-CRC forensics, and analyze_ldr for device reads/writes and semantic summaries.
    Unsupported payloads remain opaque, complete Ladder IR is returned only when every network
    decodes, and
    bad CRC or unknown framing returns an error. The workspace file is never modified.
    

    Use this for per-network meaning, decoded counts, device read/write references, timer
    settings and completeness warnings. Use read_ldr when full decoded logic or raw payloads
    are needed, or inspect_ldr for framing and CRC evidence. Bad CRC or unknown framing returns
    an error; opaque networks produce an explicit incomplete-analysis warning. Nothing is
    written or sent to a PLC.
    

    This only aligns decoded display-order networks as insert/delete/replace. It does not
    validate IR, simulate behavior or write a file: use validate_ladder, simulate_ladder or
    generate_ldr for those actions. Use read_ldr for either file's decoded network contents.
    

    Returns simplified connected IR, layout and resource/policy errors; it is not PLC syntax
    validation. To report differences between two existing .ldr files, use compare_ldr instead.
    

    This neither generates a system .ldr nor compares existing files; use generate_system_ldr
    for multi-control generation and compare_ldr for file differences. This is a
    Boolean/direct R/D model, not PLC emulation. scan_ms is required for T/C and FUN87/88/89.
    Supports the explicitly listed
    numeric/native subset; unsupported actions fail without a partial trace.
    Words use unsigned 16-bit storage. Missing X inputs reset false each scan.
    See get_capabilities simulation_model for assumptions and supported actions.
    

    Use this for a lossless round trip that preserves unknown payloads and the source file's CRC
    validity state; it does not change network logic. The source remains untouched and an
    existing output_name is rejected. Returns the new artifact link, size, SHA-256 and warnings.
    Use modify_network to insert, replace or delete logic, or generate_ldr for new Ladder IR.
    

    Use operation replace, insert or delete; index 0 is N000 and untouched raw records are
    preserved. Unlike get_capabilities, this changes program content; get_capabilities returns
    server metadata only. The source file is never overwritten.