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IMPORTANT

本專案不是 FATEK 官方產品,不會連線或下載程式到 PLC。

主要功能

  • 產生啟停、自保持、計時、計數、正反轉、星三角與順序控制。

  • 支援自訂 Ladder IR,以及多種 FATEK 原生 FUNC 編解碼。

  • 產檔前檢查 I/O、元件範圍、重複 writer、工作區政策及實際輸出 bytes。

  • 提供有限的離線掃描模型與 acceptance cases。

  • 讀取、比較、分析及安全地另存 .ldr。

  • 依使用者要求另產生 CP950/Big5 元件註解 .txt。

  • 使用本機範本檢查及產生實驗性的 .pdw 專案。

完整範圍請看功能總覽與 FUNC 支援表。

Related MCP server: OpenFab MCP

版本與執行中能力

最新版本

最新發布版為 v1.1.1;目前 main 另含尚未發行的修正。v1.1.1 改善 MCP 工具探索、 精簡回應、警告傳遞與驗證證據表達,並納入 FBs-32MC 的 PDW 範本版面。已發布內容、 目前未發行變更與下載請見 Releases 與 CHANGELOG。

Experimental features

.pdw 專案產生器仍屬實驗功能。它使用本機 FBs-20MC/32MC/40MC/60MC 範本,支援共用 Ladder 編譯、可變長度程式、分區、 中文註解與已有模組紀錄的保留/選用,但仍有格式及指令驗證限制。

查詢目前 server

呼叫 get_capabilities 可查看執行中 server 的 version、build.commit、 build.distribution_state 與 response_mode。預設是精簡回應;只有需要完整 schema 與 證據細節時才傳入 detail=true,或以 --full-responses 啟動。

快速安裝

下載原始碼並在專案目錄執行:

Windows PowerShell

powershell -NoProfile -ExecutionPolicy Bypass -File .\install.ps1

macOS / Linux

sh install.sh

安裝完成後,將 .install/mcp-config.json 或 .install/mcp-config.toml 中的 winproladder 設定加入 MCP client,再重新連線。詳細說明見安裝指南。

使用範例

直接用自然語言描述控制需求與 I/O:

X0 啟動、X1=1 停止、Y0 自保持,停止優先。驗證後產生 motor.ldr。

需要元件註解時一併說明:

另外新增元件註解:X0 是啟動按鈕,Y0 是馬達輸出。

MCP 會回傳可下載的 .ldr;明確要求註解時,另回傳 .txt。預設輸出位於 artifacts/,且不覆寫同名檔案。

驗證邊界

本專案負責離線產生、解析與驗證檔案。WinProLadder GUI 匯入、PLC 下載及實機測試由使用者在目標環境完成。離線模型通過不等於實體設備已驗證。

文件

版本內容與後續變更統一記錄在 CHANGELOG。

授權

本專案原創程式碼與文件採用 MIT License,Copyright © 2026 syrup2718。

Available Tools

23 tools
analyze_ldrA
Read-only

Explain the behavior and device usage of one existing valid .ldr file.

    Use this for per-network meaning, decoded counts, device read/write references, timer
    settings and completeness warnings. Use read_ldr when full decoded logic or raw payloads
    are needed, or inspect_ldr for framing and CRC evidence. Bad CRC or unknown framing returns
    an error; opaque networks produce an explicit incomplete-analysis warning. Nothing is
    written or sent to a PLC.
    

Inputs: path (required). Returns: object

compare_ldrA
Read-only

Compare two existing .ldr files and report their structural and CRC differences.

    This only aligns decoded display-order networks as insert/delete/replace. It does not
    validate IR, simulate behavior or write a file: use validate_ladder, simulate_ladder or
    generate_ldr for those actions. Use read_ldr for either file's decoded network contents.
    

Inputs: left_path (required), right_path (required). Returns: object

export_ldrA

Re-encode one existing .ldr into a separate new .ldr artifact.

    Use this for a lossless round trip that preserves unknown payloads and the source file's CRC
    validity state; it does not change network logic. The source remains untouched and an
    existing output_name is rejected. Returns the new artifact link, size, SHA-256 and warnings.
    Use modify_network to insert, replace or delete logic, or generate_ldr for new Ladder IR.
    

Inputs: path (required), output_name (required). Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_component_commentsA

Create only a separate CP950 WinProLadder component-comment import .txt file.

    Call this only when the user explicitly requests 新增元件註解 or component comments. It
    does not inspect, analyze, generate or modify ladder logic or PDW projects; use analyze_ldr
    to explain the logic and device references in an existing .ldr.
    Rows use REF/COMMENT/DESCRIPTION, tabs, CRLF and CP950/Big5; COMMENT is at most 16
    encoded bytes. Never overwrites a file.
    

Inputs: entries (required), output_name (required). Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_control_ldrA

Generate a new .ldr for exactly one supported control recipe in a ControlSpec.

    Never use this for multiple independent controls, ordered steps or caller-authored IR: use
    generate_system_ldr, generate_sequence_ldr or generate_ldr respectively. Supports latch,
    toggle, edges, delays, pulse, counter, direction interlock and star/delta. Physical I/O must
    be explicit; validation failure writes nothing. generate_component_comments creates only a
    separate comment-import .txt.
    

Inputs: spec (required), io_contract (required), output_name (required), acceptance, +3 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_ldrA

Compile complete Ladder IR the caller already provides into a new binary .ldr file.

    Never translate a ControlSpec, SequenceSpec or SystemSpec to call this tool; use
    generate_control_ldr, generate_sequence_ldr or generate_system_ldr. It does not design
    recipes, resolve defaults or allocate recipe resources. generate_component_comments creates
    only a separate comment .txt. Returns SHA-256, a resource link and warnings; validation
    failure writes nothing and existing files are never overwritten.
    

Inputs: ladder (required), io_contract (required), output_name (required), acceptance, +2 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_pdwA

Create a new fixed-size PDW binary by replacing one or two X-to-Y template rungs.

    Same rung count required. Only X0/X1, Y0/Y1/Y2 and NO/NC contacts supported.
    No branches, functions, comments or PLC operations. Templates are workspace-scoped.
    This generates a PDW binary; generate_component_comments produces only a separate .txt.
    Keep private templates outside Git; configure --root to their private directory.
    Return the actual binary artifact and warnings. Never overwrite.
    

Inputs: rungs (required), io_contract (required), output_name (required), template_path (required), +1 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_project_pdwA

Create or revise a PDW non-destructively by compiling Ladder IR into a new project.

    Supply an existing local PDW as template_path and a different output_name; opaque project
    settings are retained while requested program and annotations are replaced. This writes a
    variable-length PDW binary with optional embedded sections and comments;
    generate_component_comments writes only a separate comment-import .txt and cannot create a
    PDW project. Sampled FBs-20MC/32MC/40MC/60MC layouts are supported.

    Module records come from local templates.

    Match ladder.profile to the template CPU. Template must be inside workspace.
    Network.comment supports CR/LF. Section indexes refer to zero-based source networks.
    Optional embedded SECT text uses only the sampled even-byte encoding. FUNC199 and
    control flow are not generated. New files only, no PLC connection or GUI guarantee.
    module_order=null preserves all modules; [] removes them explicitly. Names copy exact
    records from the template and optional workspace-scoped module_template_paths. Order and
    duplicates are retained. Missing or conflicting records are rejected. No automatic I/O
    allocation, module parameter editing, slot-capacity or hardware compatibility validation.
    

Inputs: ladder (required), io_contract (required), output_name (required), template_path (required), +6 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_sequence_ldrA

Generate a new .ldr for dependent ordered steps defined by a SequenceSpec.

    Never use this for one control, independent controls or caller-authored IR: use
    generate_control_ldr, generate_system_ldr or generate_ldr respectively. validate_ladder
    checks existing IR and cannot derive steps. Uses native T timers or FUN87 register state for
    pause/resume, never adds X/Y, and requires an explicit clock for pulse counting. Validation
    failure writes nothing; no GUI or PLC verification is implied.
    

Inputs: spec (required), io_contract (required), output_name (required), acceptance, +3 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

generate_system_ldrA

Generate a new .ldr for two or more independent ControlSpec recipes in one SystemSpec.

    Never use this for one recipe, dependent ordered steps or caller-authored IR: use
    generate_control_ldr, generate_sequence_ldr or generate_ldr respectively. This tool
    allocates internal M/T/C, permits shared inputs, rejects explicit overlaps, checks
    acceptance and writes only a new artifact. Validation failure writes nothing. It does not
    execute existing IR or return a trace; use simulate_ladder for that.
    

Inputs: spec (required), io_contract (required), output_name (required), acceptance, +3 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

get_capabilitiesA
Read-only

Return server-wide support, policies and limits as metadata only.

    Includes build/version, generation and simulation scope, architecture policy, workspace,
    output directory and artifact delivery. detail=true expands instruction-specific limits.
    This never reads or modifies program content; use modify_network to edit one network.
    PLC access and artifact rename/delete are intentionally outside this offline server.
    

Inputs: detail. Returns: object

get_design_guideA
Read-only

Return offline workflow guidance for designing supported WinProLadder programs.

    Use this before generation to choose a control, sequence, system or custom-Ladder tool and
    to obtain acceptance-test patterns. With detail=false it returns compact control recipes,
    architecture policy and workflow; detail=true adds instruction notes, complete examples
    and the Ladder IR schema. This is not runtime capability metadata (get_capabilities),
    instruction operand evidence (get_instruction_capabilities), or manual/RTC reference data
    (get_manual_reference), and it does not validate IR or create a file.
    

Inputs: detail. Returns: object

get_instruction_capabilitiesA
Read-only

Return implemented limits and evidence for one instruction family.

    Omit family to discover valid identifiers; provide one returned identifier for its operand,
    encoding and runtime-model boundaries. Use this for implemented MCP coverage, not general
    PLC legality: get_manual_reference provides manual maxima and edition differences, while
    get_capabilities provides server-wide support. Unknown family identifiers return an error.
    

Inputs: family. Returns: object

get_ldr_artifactA
Read-only

Retrieve a generated .ldr as an embedded MCP binary resource and download link.

    Use the original output_name, including .ldr. Returns exact file bytes as base64
    with SHA-256; only reads the configured output directory. Useful when the client
    cannot access local server paths or cannot invoke resources/read directly.
    

Inputs: output_name (required). Returns: Structured result for artifact-writing and artifact-retrieval tools.

get_manual_referenceA
Read-only

Return bundled PLC-manual semantics, operand maxima and cited source pages.

    Use this to decide documented PLC legality, manual-edition differences or RTC register and
    control procedures. Use get_instruction_capabilities instead for implemented encoder and
    simulation coverage, or get_design_guide for generation workflow. This reads no project or
    PLC state and returns static reference data only.
    

Inputs: no named parameters. Returns: object

get_pdw_artifactA
Read-only

Return the exact bytes and download link for one previously generated PDW artifact.

    Use this after PDW generation when the client needs an embedded binary resource; use
    inspect_pdw to interpret project structure, or get_ldr_artifact for an .ldr. output_name
    must be the exact plain .pdw filename in the artifact directory. Missing, oversized or
    wrong-extension files return an error. This reads only and returns URI, size and SHA-256.
    

Inputs: output_name (required). Returns: Structured result for artifact-writing and artifact-retrieval tools.

inspect_ldrA
Read-only

Inspect the binary container of one existing .ldr file without decoding its logic.

    Use this for framing, record offsets, raw payload bytes and stored/calculated CRC evidence.
    It reads one workspace-scoped file and returns metadata only; it never writes or connects to
    a PLC. Use read_ldr for decoded networks or analyze_ldr for device reads, writes and
    meaning.
    Invalid framing or file constraints return an error rather than partial interpretation.
    

Inputs: path (required). Returns: object

inspect_pdwA
Read-only

Inspect the structure and metadata of one existing workspace PDW project.

    Use this for CPU/profile data, modules, sections, Chinese comments, network offsets and
    known checksums. It does not return the downloadable binary; use get_pdw_artifact for exact
    generated bytes. FUNC199 and unsupported layouts remain opaque, invalid files return an
    error, and nothing is written or sent to a PLC.
    

Inputs: path (required). Returns: object

inspect_rtc_snapshotA
Read-only

Validate a caller-supplied FATEK RTC register snapshot offline.

    Use this after obtaining R4128..R4134 externally; optionally include packed R4135 to check
    hour/minute consistency. It checks field ranges and month/day, then returns decoded fields,
    expected_R4135 and consistency when supplied. Invalid or unknown fields return an error and
    nothing is written. This server has no PLC-access tool; use get_manual_reference for RTC
    register meanings and setting procedure.
    

Inputs: registers (required). Returns: object

modify_networkA

Edit one network in an existing .ldr and write the result to a new .ldr file.

    Use operation replace, insert or delete; index 0 is N000 and untouched raw records are
    preserved. Unlike get_capabilities, this changes program content; get_capabilities returns
    server metadata only. The source file is never overwritten.
    

Inputs: path (required), index (required), operation (required), output_name (required), +2 more. Returns: Structured result for artifact-writing and artifact-retrieval tools.

read_ldrA
Read-only

Decode one existing .ldr into display-order network records and optional Ladder IR.

    Use this for decoded logic and raw payloads; use inspect_ldr for container offsets or
    bad-CRC forensics, and analyze_ldr for device reads/writes and semantic summaries.
    Unsupported payloads remain opaque, complete Ladder IR is returned only when every network
    decodes, and
    bad CRC or unknown framing returns an error. The workspace file is never modified.
    

Inputs: path (required). Returns: object

simulate_ladderA
Read-only

Simulate caller-supplied Ladder IR and return a bounded per-scan behavior trace.

    This neither generates a system .ldr nor compares existing files; use generate_system_ldr
    for multi-control generation and compare_ldr for file differences. This is a
    Boolean/direct R/D model, not PLC emulation. scan_ms is required for T/C and FUN87/88/89.
    Supports the explicitly listed
    numeric/native subset; unsupported actions fail without a partial trace.
    Words use unsigned 16-bit storage. Missing X inputs reset false each scan.
    See get_capabilities simulation_model for assumptions and supported actions.
    

Inputs: inputs (required), ladder (required), initial, scan_ms. Returns: object

validate_ladderA
Read-only

Validate one caller-supplied Ladder IR object without reading or writing .ldr files.

    Returns simplified connected IR, layout and resource/policy errors; it is not PLC syntax
    validation. To report differences between two existing .ldr files, use compare_ldr instead.
    

Inputs: ladder (required). Returns: object

Tool Schema Changelog

Recent tool additions, removals, and schema changes observed during successful MCP inspections.

Loading tool schema changelog…

    TDQS

    A4.2/5.0

    Scored across 23 tools

    Disambiguation3/5

    Descriptions are unusually careful in cross-referencing each other, but the surface contains several near-neighbor clusters: read_ldr vs analyze_ldr vs inspect_ldr vs compare_ldr, six generate_* entry points (ldr / control / sequence / system / pdw / project_pdw), and four reference tools (get_capabilities / get_instruction_capabilities / get_manual_reference / get_design_guide). The heavy 'never use this for X, use Y' phrasing is evidence that boundaries are genuinely easy to cross, even though the text does eventually disambiguate.

    Naming Consistency5/5

    Every tool is snake_case with a leading verb (read_, inspect_, analyze_, compare_, validate_, simulate_, generate_, get_, modify_, export_). Suffixes consistently name the artifact or concept (ldr, pdw, artifact, capabilities), and multi-word nouns follow the same ordering throughout.

    Tool Count4/5

    23 tools sits at the heavy end, driven by the breadth of the domain (LDR container work, PDW projects, four generation recipes, simulation, references). Each tool has a defensible niche, though the six generate_* variants and four inspect/reference variants could likely be consolidated via parameters.

    Completeness4/5

    The offline lifecycle is well covered: read/inspect/analyze/compare/validate/simulate/modify/export for .ldr, inspect/generate/artifact-fetch for PDW, plus generation and reference tools. Notable gaps are the absence of any workspace file-listing/discovery tool and of rename/delete operations, the latter explicitly declared out of scope.

    Maintenance

    ActivityActive
    ResponsivenessNo recent community issues

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