synthesize_verilog

Instructions

Implementation Reference

• src/index.ts:147-223 (handler)

  Core implementation of the synthesize_verilog tool. Performs Verilog synthesis using Yosys by creating a temp project, generating target-specific scripts (generic, ice40, xilinx), executing yosys, and returning synthesized netlist with logs.

    async synthesizeVerilog(verilogCode: string, topModule: string, target = "generic"): Promise<string> {
      try {
        const projectId = Math.random().toString(36).substring(2, 15);
        const projectDir = join(this.tempDir, `project_${projectId}`);
        await fs.mkdir(projectDir, { recursive: true });
  
        // Store project info
        this.projects.set(projectId, { dir: projectDir, type: "synthesis" });
  
        // Write Verilog file
        const verilogFile = join(projectDir, "design.v");
        await fs.writeFile(verilogFile, verilogCode);
  
        // Create synthesis script
        let synthScript: string;
        switch (target.toLowerCase()) {
          case "ice40":
            synthScript = `
  read_verilog design.v
  hierarchy -check -top ${topModule}
  synth_ice40 -top ${topModule}
  write_verilog synth_output.v
  stat
  `;
            break;
          case "xilinx":
            synthScript = `
  read_verilog design.v
  hierarchy -check -top ${topModule}
  synth_xilinx -top ${topModule}
  write_verilog synth_output.v
  stat
  `;
            break;
          default:
            synthScript = `
  read_verilog design.v
  hierarchy -check -top ${topModule}
  synth -top ${topModule}
  techmap
  opt
  write_verilog synth_output.v
  stat
  `;
        }
  
        const scriptFile = join(projectDir, "synth.ys");
        await fs.writeFile(scriptFile, synthScript);
  
        // Run Yosys
        const { stdout, stderr } = await execAsync(`yosys -s ${scriptFile}`, {
          cwd: projectDir,
          timeout: 120000,
        });
  
        let synthVerilog = "";
        try {
          synthVerilog = await fs.readFile(join(projectDir, "synth_output.v"), 'utf8');
        } catch {
          synthVerilog = "Synthesis output not generated";
        }
  
        return JSON.stringify({
          project_id: projectId,
          success: true,
          stdout,
          stderr,
          synthesized_verilog: synthVerilog,
          target,
        }, null, 2);
      } catch (error: any) {
        return JSON.stringify({
          success: false,
          error: error.message || String(error),
        }, null, 2);
      }
    }

• src/index.ts:727-748 (registration)

  MCP tool registration in listTools handler, defining name, description, and JSON input schema requiring verilog_code and top_module, with optional target.

    name: "synthesize_verilog",
    description: "Synthesize Verilog code using Yosys for various FPGA targets",
    inputSchema: {
      type: "object",
      properties: {
        verilog_code: { 
          type: "string", 
          description: "The Verilog source code to synthesize" 
        },
        top_module: { 
          type: "string", 
          description: "Name of the top-level module" 
        },
        target: { 
          type: "string", 
          description: "Target technology (generic, ice40, xilinx, intel)", 
          default: "generic" 
        },
      },
      required: ["verilog_code", "top_module"],
    },
  },

• src/index.ts:729-747 (schema)

  JSON schema for tool inputs: verilog_code (string, required), top_module (string, required), target (string, optional default 'generic').

  inputSchema: {
    type: "object",
    properties: {
      verilog_code: { 
        type: "string", 
        description: "The Verilog source code to synthesize" 
      },
      top_module: { 
        type: "string", 
        description: "Name of the top-level module" 
      },
      target: { 
        type: "string", 
        description: "Target technology (generic, ice40, xilinx, intel)", 
        default: "generic" 
      },
    },
    required: ["verilog_code", "top_module"],
  },

• src/index.ts:868-879 (handler)

  Dispatch handler in MCP callToolRequest that validates parameters and invokes the EDAServer.synthesizeVerilog method.

  case "synthesize_verilog": {
    const verilogCode = validateRequiredString(args, "verilog_code", name);
    const topModule = validateRequiredString(args, "top_module", name);
    const target = getStringProperty(args, "target", "generic");
    
    return {
      content: [{
        type: "text",
        text: await edaServer.synthesizeVerilog(verilogCode, topModule, target),
      }],
    };
  }