EDA Tools MCP Server
Server Configuration
Describes the environment variables required to run the server.
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||
Instructions
Guidance the server publishes about itself, which clients place ahead of the tool catalog so the model reads it before choosing anything.
This server publishes no instructions, or was last inspected before Glama recorded them.
Capabilities
Server capabilities have not been inspected yet.
Tools
Functions exposed to the LLM to take actions
| Name | Description |
|---|---|
| synthesize_verilogC | Synthesize Verilog code using Yosys for various FPGA targets |
| simulate_verilogC | Simulate Verilog code using Icarus Verilog |
| view_waveformB | Open VCD waveform file in GTKWave viewer |
| run_openlaneA | Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes. |
| view_gdsC | Open GDSII file in KLayout viewer |
| read_openlane_reportsB | Read OpenLane report files for LLM analysis. Returns all reports or specific category for detailed analysis of PPA metrics, timing, routing quality, and other design results. |
Prompts
Interactive templates invoked by user choice
| Name | Description |
|---|---|
No prompts | |
Resources
Contextual data attached and managed by the client
| Name | Description |
|---|---|
No resources | |
TDQS
Scored across 6 tools
Each tool has a clearly distinct purpose targeting specific EDA tasks: reading reports, running the full design flow, simulation, synthesis, viewing GDSII files, and viewing waveforms. There is no overlap in functionality, making tool selection unambiguous for an agent.
All tool names follow a consistent verb_noun pattern (e.g., read_openlane_reports, run_openlane, simulate_verilog). The naming is uniform and predictable across all six tools, enhancing usability and clarity.
With 6 tools, the server is well-scoped for EDA workflows, covering key stages from simulation to GDSII viewing. Each tool earns its place without being excessive or insufficient for the domain's typical operations.
The toolset covers core EDA operations like simulation, synthesis, and viewing, but lacks explicit update or delete tools for managing design files or results. However, the provided tools support a complete workflow from RTL to analysis, with only minor gaps.