run_openlane

Instructions

Implementation Reference

• src/index.ts:333-505 (handler)

  Core implementation of the run_openlane tool. Creates temporary project directory, writes Verilog source and OpenLane config, generates a bash wrapper script to run OpenLane in Dockerized mode with TTY workaround, executes the flow with 10min timeout, locates generated GDS file, and optionally launches KLayout viewer.

    async runOpenlane(
      verilogCode: string, 
      designName: string, 
      clockPort = "clk", 
      clockPeriod = 10.0,
      openInKlayout = true
    ): Promise<string> {
      try {
        const projectId = Math.random().toString(36).substring(2, 15);
        const projectName = `${designName}_${projectId}`;
        const projectDir = join(this.openlaneDir, projectName);
        
        // Store project info
        this.projects.set(projectId, { dir: projectDir, type: "openlane" });
  
        // Create project directory
        await fs.mkdir(projectDir, { recursive: true });
  
        // Write Verilog file
        const verilogFile = join(projectDir, `${designName}.v`);
        await fs.writeFile(verilogFile, verilogCode);
  
        // Create OpenLane config
        const configContent = {
          DESIGN_NAME: designName,
          VERILOG_FILES: [`${designName}.v`],
          CLOCK_PORT: clockPort,
          CLOCK_PERIOD: clockPeriod,
          // Additional OpenLane settings for better results
          FP_SIZING: "absolute",
          DIE_AREA: "0 0 100 100",
          FP_PDN_MULTILAYER: false,
          QUIT_ON_TIMING_VIOLATIONS: false,
          QUIT_ON_MAGIC_DRC: false,
          QUIT_ON_LVS_ERROR: false,
          RUN_KLAYOUT_XOR: false,
          RUN_KLAYOUT_DRC: false
        };
  
        const configFile = join(projectDir, "config.json");
        await fs.writeFile(configFile, JSON.stringify(configContent, null, 2));
  
        // Find Python command
        let pythonCmd = "python3";
        const pythonCandidates = [
          "python3",
          "python"
        ];
        
        for (const candidate of pythonCandidates) {
          if (await commandExists(candidate)) {
            pythonCmd = candidate;
            break;
          }
        }
  
        // Run the OpenLane command using Docker MCP approach
        console.error(`Starting OpenLane flow for ${designName}...`);
        console.error(`Working directory: ${projectDir}`);
        console.error(`This may take up to 10 minutes...`);
  
        const openlaneCmd = `${pythonCmd} -m openlane --dockerized config.json`;
        console.error(`Executing: ${openlaneCmd}`);
  
        // Create a wrapper script to handle TTY issues
        const wrapperScript = `#!/bin/bash
  set -e
  
  # Disable TTY requirements
  export DEBIAN_FRONTEND=noninteractive
  export CI=true
  export TERM=dumb
  
  # Change to project directory
  cd "${projectDir}"
  
  # Run OpenLane with script command to simulate TTY
  script -q /dev/null ${pythonCmd} -m openlane --dockerized config.json
  `;
  
        const wrapperPath = join(projectDir, 'run_openlane.sh');
        await fs.writeFile(wrapperPath, wrapperScript);
        await execAsyncWithTimeout(`chmod +x "${wrapperPath}"`, {});
  
        // Run the OpenLane command using the wrapper script
        console.error(`Starting OpenLane flow for ${designName}...`);
        console.error(`Working directory: ${projectDir}`);
        console.error(`This may take up to 10 minutes...`);
        console.error(`Using wrapper script to handle TTY`);
  
        const { stdout, stderr } = await execAsyncWithTimeout(`"${wrapperPath}"`, {
          cwd: projectDir,
          env: {
            ...process.env,
            PATH: process.env.PATH + ":/usr/local/bin:/opt/homebrew/bin"
          },
          maxBuffer: 10 * 1024 * 1024, // 10MB buffer instead of default 1MB
          timeout: 600000
        }, 600000); // 10 minutes timeout
  
        // Find the latest run directory
        const runsDir = join(projectDir, "runs");
        let latestRun = "";
        let gdsFile = "";
        
        try {
          const runs = await fs.readdir(runsDir);
          if (runs.length > 0) {
            // Sort runs by name (they include timestamps) and get the latest
            latestRun = runs.sort().reverse()[0];
            const finalDir = join(runsDir, latestRun, "final", "gds");
            
            // Find GDS file
            try {
              const gdsFiles = await fs.readdir(finalDir);
              const gdsFilesList = gdsFiles.filter(f => f.endsWith('.gds'));
              if (gdsFilesList.length > 0) {
                gdsFile = join(finalDir, gdsFilesList[0]);
              }
            } catch {
              // GDS directory might not exist
            }
          }
        } catch {
          // Runs directory might not exist
        }
  
        let klayoutResult = "";
        
        // Open in KLayout if requested and GDS file exists
        if (openInKlayout && gdsFile) {
          try {
            // Check if KLayout is available
            if (await commandExists('klayout')) {
              // Launch KLayout with the GDS file
              const klayoutCmd = `open -a KLayout "${gdsFile}" &`;
              await execAsyncWithTimeout(klayoutCmd, {}, 10000);
              klayoutResult = `KLayout launched with GDS file: ${basename(gdsFile)}`;
            } else {
              klayoutResult = "KLayout not found. Install KLayout to view GDS files.";
            }
          } catch (error: any) {
            klayoutResult = `KLayout launch failed: ${error.message}`;
          }
        }
  
        return JSON.stringify({
          project_id: projectId,
          success: true,
          design_name: designName,
          project_dir: projectDir,
          latest_run: latestRun,
          gds_file: gdsFile ? basename(gdsFile) : "Not generated",
          gds_path: gdsFile,
          klayout_status: klayoutResult,
          command_used: openlaneCmd,
          stdout: stdout.length > 2000 ? stdout.substring(0, 2000) + "...(truncated)" : stdout,
          stderr: stderr.length > 2000 ? stderr.substring(0, 2000) + "...(truncated)" : stderr,
          note: "OpenLane flow completed. Check the runs directory for detailed results."
        }, null, 2);
  
      } catch (error: any) {
        // Simple error reporting
        const errorMessage = error.message || String(error);
        console.error(`OpenLane error: ${errorMessage}`);
        
        return JSON.stringify({
          success: false,
          error: errorMessage,
          note: "OpenLane flow failed. Make sure Docker is running and try: docker pull efabless/openlane:latest"
        }, null, 2);
      }
    }

• src/index.ts:787-817 (schema)

  Input schema/JSON Schema for the run_openlane tool, defining parameters like verilog_code, design_name, clock_port, clock_period, and open_in_klayout.

  name: "run_openlane",
  description: "Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes.",
  inputSchema: {
    type: "object",
    properties: {
      verilog_code: { 
        type: "string", 
        description: "The Verilog RTL code for ASIC implementation" 
      },
      design_name: { 
        type: "string", 
        description: "Name of the design (will be used for module and files)" 
      },
      clock_port: { 
        type: "string", 
        description: "Name of the clock port", 
        default: "clk" 
      },
      clock_period: { 
        type: "number", 
        description: "Clock period in nanoseconds", 
        default: 10.0 
      },
      open_in_klayout: {
        type: "boolean",
        description: "Automatically open result in KLayout",
        default: true
      },
    },
    required: ["verilog_code", "design_name"],
  },

• src/index.ts:723-860 (registration)

  Registration of the tool list handler. The run_openlane tool descriptor is included in the tools array returned here.

  server.setRequestHandler(ListToolsRequestSchema, async () => {
    return {
      tools: [
        {
          name: "synthesize_verilog",
          description: "Synthesize Verilog code using Yosys for various FPGA targets",
          inputSchema: {
            type: "object",
            properties: {
              verilog_code: { 
                type: "string", 
                description: "The Verilog source code to synthesize" 
              },
              top_module: { 
                type: "string", 
                description: "Name of the top-level module" 
              },
              target: { 
                type: "string", 
                description: "Target technology (generic, ice40, xilinx, intel)", 
                default: "generic" 
              },
            },
            required: ["verilog_code", "top_module"],
          },
        },
        {
          name: "simulate_verilog",
          description: "Simulate Verilog code using Icarus Verilog",
          inputSchema: {
            type: "object",
            properties: {
              verilog_code: { 
                type: "string", 
                description: "The Verilog design code" 
              },
              testbench_code: { 
                type: "string", 
                description: "The testbench code" 
              },
            },
            required: ["verilog_code", "testbench_code"],
          },
        },
        {
          name: "view_waveform",
          description: "Open VCD waveform file in GTKWave viewer",
          inputSchema: {
            type: "object",
            properties: {
              project_id: { 
                type: "string", 
                description: "Project ID from simulation (required)" 
              },
              vcd_file: { 
                type: "string", 
                description: "VCD filename (default: output.vcd)",
                default: "output.vcd"
              },
            },
            required: ["project_id"],
          },
        },
        {
          name: "run_openlane",
          description: "Run complete ASIC design flow using OpenLane (RTL to GDSII). This process can take up to 10 minutes.",
          inputSchema: {
            type: "object",
            properties: {
              verilog_code: { 
                type: "string", 
                description: "The Verilog RTL code for ASIC implementation" 
              },
              design_name: { 
                type: "string", 
                description: "Name of the design (will be used for module and files)" 
              },
              clock_port: { 
                type: "string", 
                description: "Name of the clock port", 
                default: "clk" 
              },
              clock_period: { 
                type: "number", 
                description: "Clock period in nanoseconds", 
                default: 10.0 
              },
              open_in_klayout: {
                type: "boolean",
                description: "Automatically open result in KLayout",
                default: true
              },
            },
            required: ["verilog_code", "design_name"],
          },
        },
        {
          name: "view_gds",
          description: "Open GDSII file in KLayout viewer",
          inputSchema: {
            type: "object",
            properties: {
              project_id: { 
                type: "string", 
                description: "Project ID from OpenLane run" 
              },
              gds_file: { 
                type: "string", 
                description: "Specific GDS filename (optional, auto-detected if not provided)" 
              },
            },
            required: ["project_id"],
          },
        },
  
        // Add this object to the tools array, right after the view_gds tool
          {
              name: "read_openlane_reports",
              description: "Read OpenLane report files for LLM analysis. Returns all reports or specific category for detailed analysis of PPA metrics, timing, routing quality, and other design results.",
              inputSchema: {
              type: "object",
              properties: {
                  project_id: { 
                  type: "string", 
                  description: "Project ID from OpenLane run" 
                  },
                  report_type: { 
                  type: "string", 
                  description: "Specific report category to read (synthesis, placement, routing, final, etc.). Leave empty to read all reports.",
                  default: ""
                  },
              },
              required: ["project_id"],
              },
          },
      ],
    };
  });

• src/index.ts:902-915 (handler)

  Dispatch handler in the MCP CallToolRequestSchema that validates inputs and delegates to edaServer.runOpenlane method.

  case "run_openlane": {
    const verilogCode = validateRequiredString(args, "verilog_code", name);
    const designName = validateRequiredString(args, "design_name", name);
    const clockPort = getStringProperty(args, "clock_port", "clk");
    const clockPeriod = getNumberProperty(args, "clock_period", 10.0);
    const openInKlayout = args && args.open_in_klayout !== false; // Default true
    
    return {
      content: [{
        type: "text",
        text: await edaServer.runOpenlane(verilogCode, designName, clockPort, clockPeriod, openInKlayout),
      }],
    };
  }

• src/index.ts:398-415 (helper)

  Generation of run_openlane.sh wrapper script inside the handler to workaround TTY issues when running OpenLane in non-interactive environments.

        const wrapperScript = `#!/bin/bash
  set -e
  
  # Disable TTY requirements
  export DEBIAN_FRONTEND=noninteractive
  export CI=true
  export TERM=dumb
  
  # Change to project directory
  cd "${projectDir}"
  
  # Run OpenLane with script command to simulate TTY
  script -q /dev/null ${pythonCmd} -m openlane --dockerized config.json
  `;
  
        const wrapperPath = join(projectDir, 'run_openlane.sh');
        await fs.writeFile(wrapperPath, wrapperScript);
        await execAsyncWithTimeout(`chmod +x "${wrapperPath}"`, {});