aedt_validate_design
Validate Ansys Electronics Desktop designs using PyAEDT. Choose simple or full validation to check design integrity before simulation.
Instructions
Run PyAEDT simple or full design validation.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| validation_kind | No | simple | |
| args | No | ||
| kwargs | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||