Suggest Placement
suggest_placementPropose optimized PCB component placements that shorten net length, orient parts toward connections, and remove courtyard overlaps. Returns dry-run proposals with scores before applying.
Instructions
Propose an optimized PCB footprint placement that shortens net length, orients parts toward their partners, and removes courtyard overlaps. Force-directed clustering pulls connected parts together (a converter's feedback divider and decoupling caps end up hugging its IC), power/high-current nets are weighted short & direct, and each part is rotated (0/90/180/270) to face neighbours so airwires stop crossing. PCB ONLY — does not touch the schematic. DRY RUN by default: returns proposals {ref:[x,y,rot]} plus a score (HPWL before/after, overlap counts) without modifying the board. Validate via check_courtyard_overlaps(positions=proposals), then re-run with apply=true before autoroute.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| refs | No | References to move (default: every non-locked footprint on the board). | |
| align | No | Tidy the result into rows/columns (default true). Snaps near-collinear part centers onto shared row (Y) and column (X) lines so passives line up cleanly with centers aligned — like KiCad's Align Centers + Distribute. Disable for a pure shortest-wire layout. | |
| apply | No | If true, move + rotate components to the proposed positions. Default false (dry run — board untouched). | |
| bounds | No | SCOPED REGROUP: confine movable parts to this box (mm) — e.g. the area beside one IC. Combine with `refs` (that IC's passives) to regroup one cluster at a time; unlisted parts stay as anchors. Far more reliable than a whole-board run on a dense board. Default: whole board. | |
| locked | No | References to hold fixed as anchors (connectors, mounting-constrained, RF, edge parts). They still pull movable parts. KiCad-locked footprints are added automatically. | |
| rotate | No | Enable pin-facing rotation (default true). | |
| spread | No | Enable density spreading (default true). Diffuses parts across free board area so a whole-board run stays legal (few/zero courtyard overlaps) instead of over-packing into a blob. Leave on for whole-board runs. | |
| grid_mm | No | Snap proposed positions to this grid (default 0.5). | |
| margin_mm | No | Extra keepout enforced between courtyards (default 0.3). | |
| iterations | No | Force-directed relaxation passes (default 200). | |
| power_nets | No | Net-name fragments treated as high-current and pulled short & direct (case-insensitive). Defaults to common rails (VBAT, VBUS, VCC, 3V3, 5V, ...). Pass [] to disable. | |
| align_tol_mm | No | Max center spacing (mm) for parts to be pulled onto the same row/column line during align (default 1.5). | |
| power_weight | No | Pull multiplier for power nets (default 3.0). | |
| board_outline | No | Optional board containment bbox override. Default: derived from Edge.Cuts. | |
| rotation_steps | No | Candidate orientations in degrees (default [0, 90, 180, 270]). | |
| decoupling_boost | No | Extra pull for 2-pin-passive <-> multi-pin-IC links so caps/feedback parts hug their IC (default 2.0). |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |