Export 3d Cli
export_3d_cliExport PCB designs to 3D model formats (STEP, GLB, STL, PLY, BREP, XAO, VRML) using kicad-cli, with control over included layers and components.
Instructions
Export a 3D model of the PCB via kicad-cli. The format param selects the subcommand (step, glb, stl, ply, brep, xao, vrml); only flags valid for that subcommand are forwarded. STEP/glb/stl/ply/brep/xao share the geometry/include flag set (no-board-body, include-tracks/pads/zones/inner-copper/silkscreen/soldermask, fuse-shapes, fill-all-vias, component/net filters, min-distance, etc.; no-optimize-step is STEP-only); vrml uses units + models-dir/models-relative instead. Rich CLI sibling of export_3d and export_vrml. Reads the last SAVED state of the .kicad_pcb.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| force | No | Overwrite output file | |
| noDnp | No | Exclude 3D models for components with 'Do not populate' attribute | |
| units | No | Output units (VRML only; default in) | |
| format | Yes | 3D output format (selects the kicad-cli subcommand) | |
| boardOnly | No | Only generate a board with no components | |
| boardPath | No | Path to the .kicad_pcb (default: current board) | |
| defineVar | No | Project variable overrides as 'KEY=VALUE' strings | |
| modelsDir | No | Folder to store 3D models in (VRML only; empty = embed in main file) | |
| netFilter | No | Only include copper items belonging to nets matching this wildcard | |
| fuseShapes | No | Fuse overlapping geometry together | |
| gridOrigin | No | Use Grid Origin for output origin | |
| outputPath | Yes | Output 3D model file path | |
| userOrigin | No | User-specified output origin e.g. '1x1in', '25.4x25.4mm' (default unit mm) | |
| drillOrigin | No | Use Drill Origin for output origin | |
| fillAllVias | No | Don't cut via holes in conductor layers | |
| includePads | No | Export pads | |
| minDistance | No | Min distance between points to treat as separate (default '0.01mm') | |
| noBoardBody | No | Exclude board body | |
| substModels | No | Substitute STEP/IGS models in place of VRML models | |
| includeZones | No | Export zones | |
| noComponents | No | Exclude 3D models for components | |
| cutViasInBody | No | Cut via holes in board body even if conductor layers not exported | |
| includeTracks | No | Export tracks and vias | |
| noUnspecified | No | Exclude 3D models for components with 'Unspecified' footprint type | |
| modelsRelative | No | Use relative model paths with modelsDir (VRML only) | |
| noOptimizeStep | No | Do not optimize STEP file (enables writing parametric curves; STEP only) | |
| componentFilter | No | Only include component models matching this refdes list (comma, wildcards) | |
| includeSilkscreen | No | Export silkscreen graphics as flat faces | |
| includeSoldermask | No | Export soldermask layers as flat faces | |
| includeInnerCopper | No | Export elements on inner copper layers |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |