List all available KiCAD tool categories with their descriptions and tool counts. Use this to discover which tools are available via the router.

Return all tools available in a specific category. Use list_tool_categories first to find valid category names.

Search all available KiCAD tools by keyword. Returns matching tool names and their categories.

Create a new KiCAD project

Open an existing KiCAD project

Open a specific .kicad_pcb board file and refresh the MCP in-memory board state.

Reload the current or specified .kicad_pcb from disk, discarding stale in-memory board state.

Close the currently loaded KiCAD project: optionally save, then drop the in-memory board and clear session state. Use this to hand control back so the user (or the agent) can edit project files directly without the MCP later clobbering those changes on save.

Save the current KiCAD project. Refuses to overwrite the board file if its contents changed on disk since load (external edit) unless force is true.

Save the current PCB board. Refuses to overwrite external disk edits unless force=true.

Save the current PCB board to a new .kicad_pcb path.

Return whether the MCP knows the loaded board has unsaved memory changes or external disk changes.

Discard the current in-memory PCB state and reload the board from disk.

Get information about the current KiCAD project

Save a named checkpoint snapshot of the current project state (renders board to PDF and records step label). Call after completing each major step — e.g. after Step 1 (schematic_ok) and Step 2 (layout_ok). Required by the demo workflow before waiting for user confirmation.

Set the PCB board dimensions (width and height) in the specified unit.

Set the auxiliary (drill/place) origin and/or grid origin of a .kicad_pcb. The aux origin is the datum used by export_drill's drillOrigin:'plot' option and by pick-and-place / plot exports with useAuxOrigin. File-based (LoadBoard -> SaveBoard): if the board is open in the KiCad GUI, a later GUI save will overwrite this edit.

Read back the auxiliary (drill/place) origin and grid origin of a .kicad_pcb in mm.

Add a new copper or technical layer to the PCB stackup.

Set the currently active PCB layer by name (e.g. F.Cu, B.Cu).

Retrieve general information about the current PCB board (dimensions, layer count, DRC status).

Return the list of all layers defined in the current PCB board.

Draw the PCB board outline (Edge.Cuts layer) as a rectangle, rounded rectangle, circle or polygon.

Delete all Edge.Cuts graphics from the current PCB board.

Replace the current Edge.Cuts board outline with a rectangle, rounded rectangle, circle or polygon.

List PCB graphic/drawing items such as gr_line, gr_arc, gr_rect, gr_text and dimensions.

Delete a PCB graphic/drawing item by UUID.

Update common properties of a PCB graphic/drawing item by UUID.

Place a mounting hole (NPTH or PTH) at the specified position on the PCB.

Add a text label to a PCB layer (e.g. silkscreen, fab, courtyard).

Create a copper fill zone (pour) on a PCB layer for a specified net.

Return the bounding box (min/max X and Y) of all objects on the current PCB board.

Render a 2D image of the PCB using kicad-cli. Returns PNG, JPG, or SVG. Use layers to filter — e.g. ["F.Cu","B.Cu","Edge.Cuts"] for copper + outline only. Use responseMode to choose delivery: "inline" (default) — PNG/JPG rendered as an image visible to Claude; SVG returned as text. "file" — image written next to the .kicad_pcb as _2d_view.; filePath is returned. Use file mode for large boards to avoid MCP message-size limits.

Imports an SVG file as filled graphic polygons onto a KiCAD PCB layer (default F.SilkS / front silkscreen). Curves are linearised automatically. Ideal for placing a company or project logo on the board.

Place a footprint component onto the PCB at the specified position. Optionally set reference, value, footprint, rotation and layer.

Move a PCB component to a new position. Optionally update rotation or flip to a different copper layer.

Move multiple PCB components transactionally. If one reference/spec is invalid, no components are moved. Saves by default unless save=false.

Rotate a PCB component to an absolute angle in degrees.

Remove a component from the PCB by its reference designator.

Edit properties of an existing PCB component (reference, value, footprint).

Set the placement type (through_hole / smd / unspecified) and optional exclusion flags on a placed PCB footprint. The placement type controls whether the footprint is included in pick-and-place (.pos) output files. Use exclude_from_pos_files to suppress a footprint from .pos exports without changing its type.

Search for a PCB component by reference designator or value and return its position and properties.

Return all properties of a PCB component (position, rotation, layer, value, footprint).

Return all pads of a PCB component with their positions, net assignments and sizes.

Return pads for one PCB component, selected refs, or all components, including XY, layer, size and net.

Return every PCB pad attached to a net name or net code.

Return separated footprint geometry bboxes: body, pads, courtyard, keepout, fab, silk and text.

Return a list of all components on the PCB, optionally filtered by layer or bounding box region.

Return the exact XY position of a specific pad on a PCB component. Use this before routing to get accurate start/end coordinates.

Estimate ratsnest/airwire segments and lengths from current pad positions grouped by net.

Alias for get_ratsnest: estimate airwire segments and lengths by net.

Classify placement conflicts as body overlap, courtyard overlap, keepout violation, silk/text overlap or pad clearance.

Move or update a footprint Reference/Value/user text field without moving the footprint.

Place a rectangular grid array of identical components on the PCB with configurable row/column spacing.

Align multiple PCB components horizontally, vertically or on a grid with optional spacing.

Detect courtyard overlaps between footprints and (optionally) flag courtyards that extend past the board outline. Accepts a positions dict of hypothetical placements so an AI can validate a proposed move_component / place_component before committing it. Returns overlap pairs with intersection extents (mm) and per-component boundary violations.

Propose an optimized PCB footprint placement that shortens net length, orients parts toward their partners, and removes courtyard overlaps. Force-directed clustering pulls connected parts together (a converter's feedback divider and decoupling caps end up hugging its IC), power/high-current nets are weighted short & direct, and each part is rotated (0/90/180/270) to face neighbours so airwires stop crossing. PCB ONLY — does not touch the schematic. DRY RUN by default: returns proposals {ref:[x,y,rot]} plus a score (HPWL before/after, overlap counts) without modifying the board. Validate via check_courtyard_overlaps(positions=proposals), then re-run with apply=true before autoroute.

Duplicate an existing PCB component at an offset position, optionally with a new reference designator.

Cluster a board's footprints by their schematic-sheet hierarchy (the HierPlace algorithm). After sync_schematic_to_board piles every footprint at the origin, this packs each functional block together as a starting point for manual placement. File-based: reads and rewrites the .kicad_pcb on disk, so save any in-memory board edits first. Locked footprints are left in place.

Create a new net on the PCB

Route a trace segment between two XY points on a fixed layer. WARNING: Does NOT handle layer changes — if start and end are on different copper layers, use route_pad_to_pad instead, which automatically inserts a via.

Route a copper arc trace defined by start/mid/end points. Uses true PCB arc primitives when available.

Add a via to the PCB

Add a copper pour (ground/power plane) to the PCB

Delete traces from the PCB. Can delete by UUID, position, or bulk-delete all traces on a net.

Query traces on the board with optional filters by net, layer, or bounding box.

Query copper zones (filled pours) on the board with optional filters by net, layer, or bounding box. Returns zone net, layers, priority, fill state, and bounding box. Useful for auditing power planes and GND pours that query_traces does not include.

Drop GND stitching vias across the board with collision checking against every non-GND segment, via, and pad on every copper layer (PTH vias penetrate the full stackup, so missing any one layer is the classic silent-short failure mode). Three combinable strategies: grid (regular grid across the interior), around_refs (densify around named ICs), and in_zones (only place vias inside an actual GND copper zone). Supports dryRun to preview placements without writing.

Get a list of all nets in the PCB with optional statistics.

Modify an existing trace (change width, layer, or net).

Create a new net class with custom design rules, optionally assigning nets to it immediately.

Route a differential pair between two sets of points.

Refill all copper zones on the board. WARNING: SWIG path has known segfault risk (see KNOWN_ISSUES.md). Prefer using IPC backend (KiCAD open) or triggering zone fill via KiCAD UI instead.

PREFERRED tool for pad-to-pad routing. Looks up pad positions automatically, detects the net from the pad, and — critically — if the two pads are on different copper layers (e.g. J1 on F.Cu and J2 on B.Cu) automatically inserts a via at the midpoint so the connection is complete. Always use this instead of route_trace when routing between named component pads.

Copy routing pattern (traces and vias) from a group of source components to a matching group of target components. The offset is calculated automatically from the position difference between the first source and first target component. Useful for replicating routing between identical circuit blocks.

Configure PCB design rules: clearance, track width, via dimensions and courtyard requirements.

Return the current PCB design rules (clearance, track width, via sizes, courtyard settings).

Run the KiCAD Design Rule Check (DRC) on the current PCB and return violations. Optionally save the report to a file.

Create a named net class with specific clearance, track-width, via, and differential-pair rules.

Assign a net to an existing net class to apply its specific design rules.

Set per-layer design rule constraints (minimum track width, clearance and via dimensions).

Check the actual clearance between two PCB items (track, via, pad, zone or component) and report whether it meets the design rules.

Return the list of current DRC violations on the PCB, optionally filtered by severity (error, warning).

Export PCB Gerber manufacturing files to a directory. Optionally include drill files, map files and choose layer subset.

Export the PCB layout as a PDF document, optionally selecting layers, page size and colour mode.

Export the PCB layout as an SVG vector image, optionally selecting layers and colour mode.

Export the PCB as a 3D model (STEP, STL, VRML or OBJ) including optional copper, solder mask, silkscreen and component 3D models.

Export a Bill of Materials (BOM) from the PCB in CSV, XML, HTML or JSON format.

Export the schematic netlist to a file using kicad-cli. Supports KiCad XML (default), Spice (for simulation), Cadstar, and OrcadPCB2 formats. Use this when you need to write a netlist file to disk — for example to produce a SPICE file for simulation or to diff against a reference. To get net/component data inline without writing a file, use generate_netlist instead.

Export a component placement/position file through kicad-cli. This compact alias of export_pos exposes the common side, format, and unit options.

Export the PCB as a VRML 3D model through kicad-cli. This compact alias of export_3d_cli exposes the VRML-specific options.

Plot Gerber files for a PCB via kicad-cli, exposing the full Plot-dialog option set (X2, netlist attributes, DNP handling, soldermask subtraction, precision, drill-file origin, stored board plot settings, etc). Reads the board from disk, so it reflects the last SAVED state of the .kicad_pcb.

Generate drill files for a PCB via kicad-cli, exposing the full Excellon/Gerber drill option set (format, drill origin, zero suppression, oval format, units, mirror-Y, minimal header, separate PTH/NPTH files, drill map + map format). Reads the last SAVED state of the .kicad_pcb.

Export the PCB in IPC-2581 format via kicad-cli. Single-file MES/CAD interchange carrying placement, nets and BOM part data inline. The bomCol* params map schematic fields to the embedded BOM columns (e.g. internal P/N, manufacturer P/N) — useful for assembly/MES imports. Reads the last SAVED state of the .kicad_pcb.

Export the PCB in ODB++ format via kicad-cli. Single job archive (copper, drill, placement, components, nets, outline) widely used by CAM/MES/assembly. Reads the last SAVED state of the .kicad_pcb.

Generate an IPC-D-356 bare-board electrical-test netlist via kicad-cli. Consumed by flying-probe and bed-of-nails testers. Reads the last SAVED state of the .kicad_pcb.

Export the PCB in GenCAD format via kicad-cli. Assembly/test interchange format. Exposes padstack flip, unique pin/footprint shape generation, drill-file origin, and store-origin-coordinate options. Reads the last SAVED state of the .kicad_pcb.

Generate a component placement (position / pick-and-place) file via kicad-cli, exposing the full CLI option set (side, format, units, bottom-negate-X, drill-file origin, SMD-only, exclude through-hole / DNP, gerber board edge). Rich CLI sibling of export_position_file. Reads the last SAVED state of the .kicad_pcb.

Plot the PCB layout to PDF via kicad-cli, exposing the full layer-plot option set (layer + common-layer lists, mirror, refdes/value exclusion, border+title, soldermask subtraction, DNP fab-layer modes, negative, black-and-white, theme, drill shape, and single/separate/multipage output modes). Rich CLI sibling of export_pdf. Reads the last SAVED state of the .kicad_pcb.

Plot the PCB layout to SVG via kicad-cli, exposing the full layer-plot option set (layer + common-layer lists, mirror, soldermask subtraction, negative, black-and-white, theme, DNP fab-layer modes, page-size mode, fit-page-to-board, exclude-drawing-sheet, drill shape, single/multi output modes). Rich CLI sibling of export_svg. Reads the last SAVED state of the .kicad_pcb.