verilator_testbenchgenerator
Generate intelligent testbenches for Verilog/SystemVerilog modules with automatic stimulus generation, assertions, and coverage points to verify hardware designs.
Instructions
Generate intelligent testbenches for Verilog/SystemVerilog modules with automatic stimulus generation
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| targetFile | Yes | Verilog file containing the module to test | |
| targetModule | Yes | Module name to generate testbench for | |
| outputFile | No | Output testbench file path | |
| template | No | Testbench template style | basic |
| protocol | No | Protocol type for protocol-aware testbench | |
| stimulusType | No | Type of stimulus to generate | directed |
| clockPeriod | No | Clock period in time units | |
| resetDuration | No | Reset duration in time units | |
| simulationTime | No | Total simulation time | |
| generateAssertions | No | Generate assertions | |
| generateCoverage | No | Generate coverage points | |
| generateCheckers | No | Generate response checkers | |
| parseOnly | No | Only parse module, don't generate testbench |