verilator_naturallanguage
Process natural language queries about RTL simulation, debugging, and analysis to understand simulation behavior and identify issues in Verilog/SystemVerilog designs.
Instructions
Process natural language queries about RTL simulation, debugging, and analysis
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| query | Yes | Natural language query about simulation | |
| context | No | ||
| history | No |