verilator_compile
Compile Verilog/SystemVerilog design files to C++ for hardware verification and simulation using Verilator.
Instructions
Compile Verilog/SystemVerilog design files to C++ using Verilator
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| files | Yes | Verilog/SystemVerilog files to compile | |
| topModule | No | Top module name | |
| outputDir | No | Output directory for compiled files | obj_dir |
| language | No | HDL language standard | systemverilog |
| optimization | No | Optimization level | |
| trace | No | Enable waveform tracing | |
| traceFormat | No | Waveform format | vcd |
| coverage | No | Enable coverage collection | |
| threads | No | Number of threads for compilation | |
| defines | No | Macro definitions | |
| includes | No | Include directories | |
| warnings | No | Warning flags to enable | |
| suppressWarnings | No | Warning flags to suppress | |
| makeFlags | No | Additional make flags | |
| verilatorFlags | No | Additional Verilator flags |