"address validation" matching MCP servers:

MCP server that translates natural language commands into SCARA robot arm control instructions, featuring simulation mode, safety validation, and multiple transport modes (STDIO/HTTP/OAuth).

Provides AI agents with instant, structured access to electronic component datasheets, pinouts, and electrical specifications without requiring PDF uploads. It enables seamless part searching, design validation, and side-by-side component comparisons across major hardware providers.

MCP server that serves Qualcomm Yocto board specs from a git repo, enabling retrieval and validation of board specifications.

Enables secure, read-only inspection and validation of KiCad PCB boards through MCP, with deterministic routing and optional AI policy plugins.

Local serial and USB hardware access for coding agents, with typed YAML protocol commands, checksum validation, audited writes, lossless captures, hardware-free replay, and MCP App visualizations. Runs locally over stdio; live hardware use requires a serial device connected to the same machine.

Enables lossless parsing, inspection, validation, simulation, and creation or editing of FATEK .ldr ladder-logic files through local stdio MCP tools, including a user-import-verified start/stop template. New files are written to an artifacts directory so existing files and original samples are never overwritten.

Enables AI-assisted Pre820 EVE development by indexing EveApps samples and APIs to provide sample discovery, API guidance, scaffold generation, code validation, and build command generation.

Enables file-only MCP workflows for Delta DOP-B/DOPSoft 2 and DOP-100/DIAScreen HMI engineering through isolated backends and explicit source/target/plan contracts, supporting audited preview, validation, approval, application, new-only save, and diff operations while preserving unknown native bytes.

Enables interaction with Cadence Virtuoso schematics to inspect hierarchies, nets, and instance properties via SkillBridge. It provides tools for component inspection and schematic validation to ensure design integrity.

Enables agents to look up ESP32-S3 PIE instruction encodings, pipeline use/def stages, register and peripheral-address data, and to estimate instruction-sequence stalls, with every answer cited to a specific page of the official Espressif TRM or Datasheet. It explicitly reports what the primary sources do not cover rather than guessing.

Enables AI agents such as Claude Code, Cursor, and Codex to safely drive a locally installed Xilinx Vivado through 32 MCP tools spanning GUI/Tcl/attach sessions, synthesis, implementation, timing and CDC analysis, XDC/IO validation, IP inspection, VCD waveform queries, and device programming. It adds structured JSON timing evidence with baseline comparison, Chinese-language diagnostics for CRITICAL WARNINGs, environment self-checks, and evidence-driven workflow prompts that gate each FPGA design stage.