formal_prove
Proves SystemVerilog assertions embedded in RTL using SymbiYosys, supporting bounded or inductive verification and returning concrete outcomes like PROVEN or FAILED with counterexamples.
Instructions
Proves SystemVerilog assertions embedded in RTL with SymbiYosys (smtbmc+z3), bounded (bmc) or inductive (prove). Returns PROVEN, FAILED with counterexample asserts, UNKNOWN, ERROR, or TIMEOUT. Author properties first with rtl_generate_assertion (mcp-rtl-review); a passing lint does not mean properties hold.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory. | |
| mode | No | Bounded check to depth (bmc) or full induction attempt (prove). Default: bmc. | |
| depth | No | Bound depth in [1, 100] (default: 10). Deeper bounds cost solver time. | |
| defines | No | Preprocessor defines for the read step, e.g. ["FORMAL"] to enable `ifdef FORMAL assertion blocks (iverilog cannot parse SVA, so guard solver-only constructs). | |
| timeout_ms | No | Maximum task time in milliseconds (default: 300000). | |
| top_module | Yes | Top module name. | |
| keep_workdir | No | Keep the SBY work directory for trace inspection (default: false). | |
| verilog_sources | Yes | RTL files containing the design and embedded assert properties. |