formal_lint_sva
Elaborates RTL with embedded SVA via Yosys to report syntax and elaboration errors with file:line diagnostics, serving as a pre-check before formal proof.
Instructions
Elaborates RTL with embedded SVA in Yosys to catch syntax and elaboration errors before solver time. Reports file:line diagnostics. Does not prove anything; use formal_prove for verdicts.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"verilog_sources": "<verilog_sources>",
"top_module": "<top_module>"
},
"name": "formal_lint_sva"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| cwd | No | Optional working directory. | |
| top_module | Yes | Top module name. | |
| verilog_sources | Yes | RTL files to elaborate. |