cocotb_generate_runner
Generate a deterministic Cocotb simulation Makefile for a Verilog DUT and Python test module, specifying sources, top-level, and simulator for immediate execution.
Instructions
Generates a deterministic, standard Cocotb simulation Makefile for a given Verilog DUT and Python test module.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"verilog_sources": "<verilog_sources>",
"toplevel": "<toplevel>",
"python_module": "<python_module>"
},
"name": "cocotb_generate_runner"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| toplevel | Yes | Top-level Verilog module name. | |
| simulator | No | Simulator backend (default: 'icarus'). | |
| python_module | Yes | Python test module name (without .py). | |
| verilog_sources | Yes | List of Verilog source files. |