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    • A
      license
      A
      quality
      D
      maintenance
      Enables AI assistants to perform Electronic Design Automation (EDA) tasks including Verilog synthesis, simulation, ASIC design flows, and waveform analysis through a unified interface.
      6
      ISC
    • A
      license
      A
      quality
      B
      maintenance
      Enables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.
      4
      10 npm
      Apache 2.0
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI coding agents to safely drive a locally installed Xilinx Vivado FPGA flow, covering session control, synthesis, implementation, timing and CDC analysis, XDC constraints, IP inspection, waveform queries, and device programming with structured, evidence-based diagnostics.
      -
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI coding agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado through 32 curated tools covering sessions, synthesis, implementation, timing and CDC reports, XDC, IP, waveforms, and device programming. It also provides structured timing evidence with baseline comparison, offline VCD queries, environment self-diagnostics, and evidence-driven workflow prompts.
      -
    • A
      license
      A
      quality
      D
      maintenance
      Provides AI assistants with a complete FPGA toolchain for HDL linting, simulation, synthesis, and place-and-route across various hardware targets. It features a GitHub-backed IP core registry that enables users to search for and import MIT-licensed cores directly through their chat interface.
      15
      1
      MIT
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables Claude Code, Cursor, Codex, and other AI agents to safely drive a locally installed Xilinx Vivado through 32 tools spanning GUI/Tcl/attach sessions, synthesis, implementation, timing, CDC, XDC, IP, waveforms, and device programming. It adds structured timing evidence with baseline comparison, offline VCD queries, evidence-driven workflow prompts, and read-only environment self-diagnostics.
      -