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VLSI Formal Verification MCP Server

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    • A
      license
      A
      quality
      B
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      Enables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.
      4
      11 npm
      Apache 2.0
    • A
      license
      A
      quality
      D
      maintenance
      Enables AI assistants to perform Electronic Design Automation (EDA) tasks including Verilog synthesis, simulation, ASIC design flows, and waveform analysis through a unified interface.
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    • A
      license
      C
      quality
      F
      maintenance
      Enables RTL simulation and hardware verification with Verilator through automatic testbench generation, natural language queries about simulations, waveform analysis, and protocol-aware testing for Verilog/SystemVerilog designs.
      4
      4
      MIT
    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI coding agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado through 32 curated tools covering sessions, synthesis, implementation, timing and CDC reports, XDC, IP, waveforms, and device programming. It also provides structured timing evidence with baseline comparison, offline VCD queries, environment self-diagnostics, and evidence-driven workflow prompts.
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    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI agents to drive a locally installed Xilinx Vivado through 32 curated tools covering sessions, synthesis, implementation, timing and CDC analysis, XDC constraints, IP inspection, waveform queries, and device programming, with structured evidence, environment self-checks, and evidence-gated workflow prompts. Supports GUI, headless Tcl, and attach session modes.
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    • F
      license
      Not graded
      quality
      A
      maintenance
      Enables AI agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado through 32 curated tools spanning sessions, synthesis, implementation, timing, CDC, XDC, IP, waveform inspection, and device programming. It also provides structured timing evidence with baseline comparison, bounded offline VCD queries, environment self-diagnosis, and Chinese-language diagnostics for timing and CRITICAL WARNING issues.
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